An address extending control circuit is disclosed which is provided with a memory having a memory capacity larger than that assignable with the content of an address register. The memory area of the memory is divided into a common block and a plurality of segment blocks of variable capacity. In a certain processing, the common block and any one of the segment blocks are utilized in pairs, thereby to obtain an extended address. To this end, an address extending address register capable of selecti...

Priority interrupt apparatus includes a level priority network, a plurality of priority networks, and selector circuits, each corresponding in number to the number of channel sources operative to generate interrupt requests. Each priority network receives requests signals corresponding to different types of possible event signals requiring attention and produces a type code designating the highest priority event from the channel associated therewith. The priority is established in accordance wit...

This disclosure relates to a storage system employing a serial periodic memory as the storage mechanism. The storage mechanism has one or more control and access ports which control data transmission to and from the storage mechanism, each port including input and output devices associated with a data track of the storage mechanism. A queue shift register is coupled between the input and output devices to receive previously stored information characters which are to be temporarily held when newl...

Scanned image data is compressed and stored in a central processing unit. An image for display is recalled, decompressed, and then recompressed for refresh storage for a CRT display device. The refresh compressed image is recalled when necessary for display and refresh, and directed through a plurality of parallel operated decompressors and refresh buffers to drive the display unit. An unfilled compressed refresh image store is filled with zeros to complete the display with an all white scan. In...

An information transferring apparatus disposed between first and second information processing units comprises a first-in first-out stack, a first information line for transferring information from the first information processing unit to the first-in first-out stack, a second information line for transferring information from the first-in first-out stack to the second information processing unit, a third information line for transferring information from the second information processing unit t...

Disclosed is a system and method for interleaved printing of letters and envelopes in an unattended manner. The system includes a memory for storing in a first portion thereof, text codes and control codes corresponding to the constant text of a form letter and envelope to be printed. As required, one or more blocks of variable data are written into the memory succeeding the form letter and envelope. The system is operative to output the contents of the memory to a printer while merging the vari...

A digital signal processor adapted for use in small, lightweight radar-guided missiles. The processor includes a scratch pad register section, an arithmetic-logic unit and a control section arranged to enable data stored in two different storage elements included in such register section to be operated on by the arithmetic-logic unit, the result of such operation to be stored in a third storage element included in the register section and the contents stored in a program counter register to be i...

An information transfer control system for controlling the information transfer between a data processor and an input/output device is disposed between the data processor and the input/output device. The information transfer control system comprises a first-in/first-out stack for temporarily storing transferring information being transferred, an up/down counter with a preset function for selectively designating the address lines desired of the stack through a decoder, and a register for setting ...

A register control instruction is added in a stored program computer and uses the same OP code as used for an existing storage instruction. A non used bit state in the existing storage instruction identifies the instruction as a register control instruction rather than a storage instruction and causes logic to generate a control signal for inhibiting the storage operation whereby the storage address is used for addressing a register instead of storage and data is transferred to or from the addre...

An initial input list in a series of sequential dependent input lists is clocked through a first sort stack and written into a first buffer as Q groups of P numbers each. The P numbers are in numerical order within each group with the smallest number in the first location of each group. The first number in each group is loaded into a second sort stack which arranges them in numerical order, causing the smallest number in the input list to form the first number in the initial output list. A repla...