A threshold comparator for use with a dual slope A/D converter has its input potential established at its threshold potential during auto-zeroing. Potential offset means is included in the auto-zero feedback loop around the integrating and output amplifiers of the A/D circuit. Bias current applied to the potential offset means substantially tracks current passed in the comparator so that the potential developed by the potential offset means substantially tracks the threshold potential of the com...

A driver circuit to limit the di/dt downgoing transition to a desired value employs an active feedback path. The driver circuit utilizes a Schottky Barrier Diode as a current bleed to limit the base current of the drive circuit transistor. The active feedback path includes a normally conductive transistor which turns off when the output falls to a predetermined level. Elimination of the active feedback path in this condition insures maximum DC drive.

A parallel-serial converter comprises a plurality of selection-delay unit circuits. The unit circuit selectively receives an output signal from the immediately preceding unit circuit and one of a plurality of input parallel signals and shifts the selectively received signal to the immediately succeeding unit circuit. The selection-delay unit circuit is only formed of three transfer gates and two inverters in order to reduce a chip size and save power consumption.

An address buffer circuit for comverting an address signal (A.sub.i) of a TTL level into an address signal (A) of a MOS level an its inverted signal (A) comprising: a pre-amplifier (P-AMP) for receiving the address signal having a TTL level; a main amplifier (M-AMP) comprising a flip-flop (FF.sub.3), a circuit for defining the operation of the flip-flop (FF.sub.3); and an output circuit (OUT) comprised of another flip-flop (FF.sub.4) for producing the address signals of a MOS level. In the pre-a...

An insulated gate field-effect transistor (MOS.multidot.FET) formed as a basic element of an integrated circuit formed together with a substrate bias circuit in a semiconductor substrate having negative potential. In the substrate bias circuit, semiconductor regions (p.sup.+ -regions) having impurity concentrations higher than that of the semiconductor substrate (p-type) are formed between the semiconductor regions (n.sup.+ -region) and the semiconductor substrate (p-type) to form n.sup.+ p.sup....

A buffer circuit (10) receives a TTL input signal at an input node (12) and produces an MOS logic signal at an output node (38). A capacitor (22) is precharged by a precharge signal (PC) to a high voltage state and a control node (32) is precharged to a high voltage state. An input transistor (14) receives a reference voltage which is a function of the levels of the TTL input. When the TTL input is high the transistor (14) is nonconductive thereby maintaining the charge at the control node (32) ...

The arbitration circuit for granting control of a shared resource to one of a plurality of ports based upon a predetermined scheme of priority includes a plurality of input flip-flops for receiving request signals from the plurality of ports. If any of the ports have requested control, the input flip-flops are latched. A priority signal is generated indicating which of the ports has priority. This is accomplished by a second plurality of delay type flip-flops which are then latched. Additional c...

A gamma ray scintillation coincidence detection circuit having four inputs connected to two gating configurations, fed by gamma ray detector units. Detection in any one of the four inputs develops a disabling signal in one signal path leading to an AND gate. Detection in any two of the four inputs results in a system output in another signal path. When any input goes high, the AND gate is disabled after a predetermined settable time delay T. If a second input goes high before the expiration of t...

A CMOS integrated circuit is made compatible with TTL input signals. A regulator operates the CMOS gates in an array at a voltage that is slightly lower than the supply. The regulator sense circuit is made responsive to an operating gate and to a TTL bias reference. Accordingly, the regulator will compensate for changes in ambient conditions and manufacturing variations so that the gate array devices will reliably respond to TTL level switching signals.

An active pull-up circuit for use in a sense amplifier or the like, comprises an enhancement type MIS transistor, a MIS capacitor controlled by a clock signal, and a depletion type MIS transistor controlled by another clock signal (.phi..sub.2 '). In this circuit, the two clock signals are bilevel signals having potentials which are the same as potentials of two power supplies.