A method and apparatus for increasing the data rate and providing antenna diversity using multiple transmit antennas is disclosed. A set of bits of a digital signal are used to generate a codeword. Codewords are provided according to a channel code. Delay elements may be provided in antenna output channels, or with suitable code construction delay may be omitted. n signals represent n symbols of a codeword are transmitted with n different transmit antennas. At the receiver MLSE or other decoding...

A non-iterative technique for calculating the remainder of modulo division, which requires significantly fewer operations than the traditional iterative technique for the same calculation. The number of calculations required in the present invention is independent of the number of bits of the divisor in the modulo operation. Two requirements of the non-iterative technique are that the value of the divisor D should be equal to 2.sup.n-1 (where n is the number of bits of the divisor D) and the val...

An apparatus, system, and method for testing packet-based semiconductor devices by using simplified test data packets. Simplified test data packets are generated by conventional memory testers in one format. The simplified test data packets are realigned to another, different format by test mode circuitry located on an integrated circuit chip, test interface, or tester prior to testing the memory device. The test method potentially reduces the number of pieces of data which must be generated usi...

A computer data signal comprises a first code group and a second code group. The first code group has a first symbol and an error detection code for the first symbol. The second code group has a second symbol and an error correction code. The error correction code provides error correction for a third symbol that includes the first symbol and the second symbol.

An information recording medium includes a disk information area; a user area including a plurality of sectors; and a spare area including at least one sector which, when at least one of the plurality of sectors included in the user area is a defective sector, is usable instead of the at least one defective sector. The spare area is located radially inward from the user area. A physical sector number of a sector to which a logical sector number "0" is assigned, among the plurality of sectors inc...

A memory mapping method for mapping a data array into a memory. The memory mapping method provides the two-directional access in the data array. The memory mapping method first equally divides each row of the data array into some basic units based on the number of the columns of the data array. Next, a predetermined number of adjacent basic units in the same column are arranged into a basic memory block. Finally, the basic memory blocks are mapped into the memory.

A method for locating a failure of a communication line according to self-adjusted priorities of the test points in the order of high failure probability in a communication line management system, includes the steps of organizing the test points, information on the test history of the test points, and test point search priorities (TSPs) representing the priorities of the test points in the order of high failure probability into a test database, searching the test database to determine the testin...

A write driver circuit includes a drive circuit having a first drive node adapted to receive a first voltage, a second drive node, an input adapted to receive a data signal, and an output. The drive circuit couples the output to the first voltage node when the data signal has a first logic voltage, and couples the output to the second drive node when the data signal has a second logic voltage. A test circuit has an input adapted to receive a test mode signal, and an output coupled to the second ...

A system and method for detecting and rectifying a proscribed non-complementary output from a complementary logic circuit. A complementary logic circuit having a true tree and a complement tree is provided. The true tree produces a true signal utilized to generate a true output signal from the complementary logic circuit. The complement tree produces a complement signal utilized to generate a complement output signal from the complementary logic circuit. Logic means coupled to the output of the ...

A method of testing and/or repairing a memory device having two arrays of memory cells arranged in rows and columns. Sense amplifiers shared by the arrays are selectively coupled by isolation transistors to the digit lines of respective columns in each array. The sense amplifiers and isolation transistors are controlled to sequentially writing known data bits to a plurality of rows in each of the arrays. The rows in the first and second arrays remain activated for a testing interval of sufficien...