A semiconductor device has a structure reducing resistances to a high frequency current. The semiconductor device includes a semi-insulating substrate, a first n-type layer made of a compound semiconductor, and a first p-type layer made of a compound semiconductor in which a signal current flows in a lateral direction, parallel to the semi-insulating substrate. The first p-type layer is sandwiched between the semi-insulating substrate and the first n-type layer. A second n type layer made of a c...

A SMD-type LED with high heat dissipation efficiency and high power includes a base with a post arranged and integrated on the center thereof and a slot on top of the post. At least one contact hole is arranged on bottom of the base for connecting with an external heat sink so as to achieve better heat dissipation. The slot is used for accommodating a LED chip that is electrically connected with a circuitry extension device through two electrical contacts. The LED chip is electrically connected ...

A nanowire includes a single crystalline semiconductor material having an exterior surface and an interior region and at least one dopant atom. At least a portion of the nanowire thermally switches between two conductance states; a high conductance state, where a high fraction of the dopant atoms is in the interior region, and a low conductance state, where a lower fraction of the dopant atoms is at the interior region and a higher fraction of the atoms is at the exterior surface. A method to se...

This invention offers a ROM in which a user can program his digital data. In a memory cell array of the ROM, in which a plurality of interlayer insulation layers and a plurality of metal layers (including a bit line which makes an uppermost layer) are alternately stacked over each memory transistor, an insulation layer is formed on a tungsten plug in a first contact hole provided in a first interlayer insulation layer. The ROM is programmed by writing digital data "1" or "0" in each of the memor...

A white light emitting device and method that generate light by combining light produced by a white light source with light produced by at least one supplemental light emitting diode (LED). The supplemental light can be used to adjust one or more properties of the generated light. Adjustments can be made to the generated light based on feedback.

A light source assembly includes a vapor chamber, which has an electrical circuit installed in the top surface, an insulation layer covered in between the top surface of the vapor chamber and the electrical circuit, and light emitting diodes installed in the top surface directly of the vapor chamber and electrically connected to the electrical circuit for producing light upon connection of electricity to the electrode circuit means and the vapor chamber, and a heat sink installed in the bottom s...

A semiconductor device includes: a semiconductor substrate including a first semiconductor layer, an insulation layer and a second semiconductor layer, which are laminated in this order; a trench penetrating both of the second semiconductor layer and the insulation layer and reaching the first semiconductor layer; and a third semiconductor layer. The trench has a ring shape on a principal surface of the substrate so that a part of the second semiconductor layer and a part of the insulation layer...

A memory cell, memory cell arrangement, and method for producing a memory cell arrangement is described where electric charge carriers can be introduced from a trench structure, which delivers charge carriers, into a charge storage area by applying a predefined electrical potential to the cell. The memory cell provides for programming with a reduced energy requirement

A SOI (silicon on insulator) single crystalline chip structure is provided. The SOI chip structure has a first silicon layer for at least one SOI device to be placed thereon, at least one buried oxide area with a predetermined depth placed at a predetermined position of the first silicon layer in order to enable the first silicon layer to have at least two different silicon layer thicknesses. The buried oxide area is filled with a silicon oxide material serving as an insulating area, and a secon...

A p well serving as a channel region of a MOSFET is formed on one side of an n.sup.- layer and an n.sup.+ drain region is formed on the other side. Above the n.sup.- layer, a plurality of first floating field plates are formed with a first insulating film interposed therebetween. A plurality of second floating field plates are formed thereon with a second insulating film interposed therebetween. Assuming that the thickness of the first insulating film is "a" and the distance between the first fl...