In a cache memory of a set associative type, a cache-miss rate measuring circuit 140 measures the cache-miss rate during way access operation, the way number control circuit 150 determines the number of ways to be accessed based on a change of the measured cache-miss rate and transfers the determined information about the ways to be accessed to the power control circuit 160. The cache memory controls as follows: When the cache-miss rate is decreased under the condition that the number of ways is...

An electronic circuit used in the control and operation of a mass storage system (30) is provided that includes an SSD channel (10), and a control circuitry (11) having a microprocessor (28) and a read only memory (ROM) (29). During an initialization routine, microprocessor (28) and the ROM (29) of the control circuitry (11) provide operational parameters to the SSD channel (10) through a data/parameter path (13). The SSD channel (10) receives these operational parameters and stores them in a pa...

A method and system of implementing a cache coherency mechanism for supporting a non-inclusive cache memory hierarchy within a data processing system is disclosed. In accordance with the method and system of the invention, the memory hierarchy includes a primary cache memory, a secondary cache memory, and a main memory. The primary cache memory and the secondary cache memory are non-inclusive. Further, a first state bit and a second state bit are provided within the primary cache, in association...

An improved method and apparatus for managing real pages, also called physical pages, and virtual pages, also called logical pages, in a virtually indexed cache that is implemented as two physical caches. A list of free real pages that is a doubly linked list with a single anchor in addition to the free real pages is created. The pages are sequentially associated with each other using two sets of pointers. A set of forward pointers are used with the first pointer connecting the anchor page to th...

A voter provided in combination with a plurality of prefetch predictors provides improved prefetch performance. In one embodiment, the voter determines which of the prefetch predictors is making more accurate predictions, and uses predictions of the more effective prefetch predictor to prefetch data into a buffer for use in satisfying cache misses. A voting prefetch engine advantageously improves cache performance, and therefore processor performance, by reducing cache misses more than cache mis...

A system and method for selective write protection for a non-volatile memory device which comprises a superset of the existing JEDEC 21-C standard and in which user definable portions of a non-volatile memory device can be write protected instead of only the entire device. The write-protection technique of the present invention can be selectably enabled or disabled dynamically as determined by a user. Moreover, the system and method of the present invention provides for storage of the device wri...

Allocation circuitry for allocating entries within a set-associative cache memory is disclosed. The set-associative cache memory comprises N ways, each way having M entries and corresponding entries in each of the N ways constituting a set of entries. The allocation circuitry has a first circuit which identifies related data units by identifying a probability that the related data units may be successively read from the cache memory. A second circuit within the allocation circuitry allocates the...

A cache memory having a mechanism for managing offset and aliasing conditions is disclosed. In accordance with a preferred embodiment of the invention, the cache memory comprises a first directory circuit, a second directory circuit, a multiple number of most recently used bits, and a multiple number of set/reset circuits. The first directory circuit, having multiple caches lines, is utilized to receive partial effective addresses. The second directory circuit is utilized to receive an output fr...

In a memory control apparatus which has a main memory constructed by a plurality of memory areas and a cache memory which can be accessed at a speed higher than that of the main memory and in which the main memory or the cache memory is accessed in response to a memory access request from an access request side and data is read out and transferred to the access request side, an accessing speed of every plurality of memory areas in the main memory is identified and an area that is cachable for th...

Nonvolatile memory devices and methods include an array of nonvolatile memory cells which are arranged in a plurality of rows and a plurality of columns. A plurality of word lines are also included, a respective one of which is connected to the nonvolatile memory cells in a respective one of a plurality of columns. A plurality of lockable cells are also included. A respective one of the lockable cells is connected to a respective one of the plurality of word lines. Each of the lockable cells sto...