Methods and apparatus are provided for sigma-delta delay control in a Delay-Locked-Loop that employs a delay line to generate a clock signal based on a reference signal. A first value is generated if a clock signal has a time lead relative to a reference signal; and a second value is generated if a clock signal has a time lag relative to a reference signal. The first and second values are accumulated to generate an N bit digital word; and the N bit digital word is reduced to an M bit digital wor...

The invention relates to an apparatus for precise modulation of signal phase and signal delay, respectively, and signal amplitude, comprising a first fixed-delay device having its input coupled to an input signal, a first variable delay device having its input coupled to said input signal and having a control input for delay adjustment, a first amplitude control device in series with the first variable delay device, providing at its output an amplitude controlled signal and having a control inpu...

Current feedback amplifiers circuits that generate common mode (CM) and/or differential mode (DM) currents are provided herein. This description is not intended to be a complete description of, or limit the scope of, the invention. Other features, aspects, and objects of the invention can be obtained from a review of the specification, the figures and the claims.

A geometric ladder circuit produces a transfer function having substantially uniform steps measured in dB. Where the ladder has a plurality of substantially identical resistor rungs of a first resistance, one stile that is a conductor connecting the rungs, and another having a series of substantially identical resistors of a second resistance, then for identical currents injected at different rungs, the output signal at an end of the ladder is attenuated by a number of substantially equal steps,...

A method and apparatus for capacitance multiplication using two charge pumps. A first charge pump (206) provides a current signal (I.sub.216) that is first conducted by a resistor (310) of an RC network and then split into three current paths prior to being conducted by a capacitor of the RC network. A first current path provides current to the capacitor (306) of the RC network from node (320). A second current path multiplies the current conducted by capacitor (306) by a first current multiplic...

A clock distribution network for clock distribution in an integrated circuit (IC) using digital feedback for skew compensation and jitter filtering. In an embodiment, a number of clock processor nodes are distributed throughout the clock distribution network on the IC at respective local clock regions. A master clock generator generates a master clock for distribution to the clock processor nodes, via the clock distribution network, to compensate clock skew and filter clock jitter locally at the...

A phase detector generates a first output signal if a feedback clock signal leads a reference clock signal by more than a first time. The phase detector generates a second output signal if the feedback clock signal lags the reference clock signal by more than a second time. If the feedback clock signal either leads the reference clock signal by less than the first time or lags the reference clock signal by less than the second time, neither output signal is generated. The phase detector may be u...

A technique for extending the size of a power transistor beyond one integrated circuit is disclosed. An example apparatus includes a first integrated circuit chip having a first switch, which includes first, second and third terminals. The first integrated circuit chip further includes a first driver circuit having an input and an output. The first integrated circuit chip also has a first control circuit coupled to output a first control signal. A second integrated circuit chip is included, whic...

A signal detector includes, in part, first and second peak detectors, a comparator and an amplifier. The first peak detector generates a first signal in response to receiving an incoming signal. The second peak detector generates a second signal in response to receiving a threshold signal. The comparator generates an output signal representing the detected signal in response to the first and second signals. The amplifier amplifies the difference between the second signal and a reference voltage ...

A current source apparatus includes a first MOS transistor having a drain serving as current input terminals with the gate connected to the drain, a first switch connected to the source of the first MOS transistor, a second MOS transistor having a drain serving as a current output terminal, a second switch connected to the source of the second MOS transistor, a third switch having one end connected to the gate of the first MOS transistor, and the other end connected to the gate of the second MOS...