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Results for ASSISTANT_EXAMINER: nguyen thanh t
Showing 1 - 10 of 598
A system for combining a plurality of video signals and various forms of still imagery such as text or graphics into a single high resolution display is disclosed. The inventive system utilizes a multiport memory and a key based memory access system to flexibly compose a multiplicity of video signals and still images into a full color high definition television display comprising a plurality of overlapping windows.
A method is provided for fabricating a nitride layer of the semiconductor integrated circuit on a semiconductor substrate in a processing chamber. Source gases are applied to the processing chamber and a first nitride layer is deposited over the semiconductor substrate according to the source gases. The source gases are discontinued and the processing chamber is pumped out. Source gases are again applied to the processing chamber and a second nitride layer is deposited upon the first nitride lay...
A semiconductor manufacturing process in which a single crystal silicon semiconductor substrate is immersed in an oxidation chamber maintained at a first temperature preferably between 400.degree. and 700.degree. C. for a first duration. During the first duration, the oxidation chamber comprises a first ambient gas of N.sub.2 or Argon. Thereafter, the ambient temperature within the oxidation chamber is ramped to a second temperature in the range of approximately 600.degree. to 1100.degree. C. NH...
A method of fabricating high step alignment marks on a twin-well integrated circuit. An alignment mark photoresist pattern is formed overlaying the nitride layer using lithography technique. The nitride layer is partially etched to form a nitride alignment pattern using the alignment mark photoresist pattern as a mask. After the formation of N-well and P-well regions using lithography technique, the N-doped and P-doped impurities are subject to a thermally drive in process to activate and form N...
A layer of reduced stress is formed on a substrate using an HDP-CVD system by delaying or interrupting the application of capacitively coupled RF energy. The layer is formed by introducing a process gas into the HDP system chamber and forming a plasma from the process gas by the application of RF power to an inductive coil. After a selected period, a second layer of the film is deposited by maintaining the inductively-coupled plasma and biasing the plasma toward the substrate to enhance the sput...
A method for depositing an aluminum film limits the growth of voids and notches in the aluminum film and forms and aluminum film with a reduced amount of voids and notches. The first step of the method is to form an underlying layer upon which is deposited an aluminum film having a first thickness. The surface of the aluminum film is then exposed to a passivation species which coats the aluminum grains and precipitates at the grain boundaries so as to prevent grain movement. The exposure of the ...
A method for forming an oxynitride gate dielectric layer (202, 204) begins by providing a semiconductor substrate (200). This semiconductor substrate is cleaned via process steps (10-28). Optional nitridation and oxidation are performed via steps (50 and 60) to form a thin interface layer (202). Bulk oxynitride gate deposition occurs via a step (70) to form a bulk gate dielectric material (204) having custom tailored oxygen and nitrogen profile and concentration. A step (10) is then utilized to ...
A method of forming a viahole in an interlayer insulating film without the formation of irregularities on a side wall of the viahole. The method includes a first step of forming a viahole in an interlayer insulating film having a multi-layer structure of plural kinds of insulating layers; a second step of forming a side wall film on a side wall of the viahole; and a third step of removing a native oxide film formed on a bottom portion of the viahole by etching.
The uniformity of the thickness of a deposition layer, generated by a chemical vapor deposition (CVD) process, on a semiconductor wafer is enhanced by providing an undercoating on the deposition chamber. The undercoating is formed at a deposition rate significantly faster than the deposition rate of the material on the wafer. A thin precoat is typically formed over the undercoating. Another method of providing uniformity of thickness includes altering the temperature of the wafer or a series of ...
A method for forming dual damascene metallic structure that utilizes the formation of a protective photoresist layer at the bottom of a vertical window to prevent damages to a device region in the substrate when subsequent etching operation is carried out to form a horizontal trench pattern. The protective photoresist layer at the bottom of the vertical window is formed by irradiating the photoresist layer with a dose of radiation having energy level insufficient to chemically dissociate the pho...
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