A dual deadman timer circuit functions to reset a dual mode microprocessor in the event of loss of program control. The microprocessor has high and low power requirements corresponding to its two operating modes, and the deadman timer circuit also adjusts the output power level of an associated two-level power supply to ensure that sufficient power is available for the full operation of the microprocessor during reset. The deadman timer functions during both microprocessor modes and includes two...

An arbitration controller providing for equal priority sharing of duplicate copy resources by a duplex plurality of central processing units. Conflicts resulting from simultaneous requests from several CPU's for access to the common resource are resolved at a high rate of speed. In addition, an approximately statistically equal probability is maintained for access of the common resource by all the central processing units.

A electronic digital processor system input/output circuitry including several input/output data ports where each port contains receiving circuitry to receive bit data from bit data pads and transmitting circuitry to transmit bit data to the data bit pads and control circuitry that provides for a configuration where one input/output port may respond to the address of another input/output port, allowing the second input/output port to perform other functions. This capability would allow a user to...

A system for converting sequentially received data words, in the form of successively received groups of data words, into an interleaved output data word sequence, with each group of received data words consisting of T successive series of R data words. The system comprises N memories, each having W words locations, where W.multidot.N.gtoreq.T.multidot.R and where the N memories form a single memory matrix which is employed to process every group of received data words. Writing logic is provided...

An interactive data retrieval apparatus in which a data base store is searched by content using search keys entered by an operator. Dedicated hardware includes a plurality of search modules and apparatus for clocking the byte-wide data stream read from the data store through successive search modules. In each module, the data is compared with an entered search key. When a match is found between the data stream and the search keys, the data record is displayed to the operator. The apparatus can d...

An electronic postal meter has a control unit, an accounting unit and a printing unit, each incorporating a CPU having a separate crystal controlled clock. Communication between the units is serial character asynchronous, bit synchronous, in message form, with the bits of the messages being timed in accordance with a given schedule for synchronous control. The messages themselves, upon receipt by a receiver, are returned bit by bit to the transmitter, for checking, whereupon the transmitter send...

In order to simulate an instantaneous temperature-rise of a thyristor through which flows a current (I), this device takes the mean value (VM) of that current and squares the effective value (EC) thereof. An image of the dissipated power obtained at the output of an adder (S) is applied to devices (K.tau.ra, K.tau.br, K.tau.jb) for simulating radiator-environment, housing-radiator and junction-housing thermal time-constants, respectively. An adder (S.sub.1) provides the image i (.DELTA..theta.) ...

A memory system for simultaneously extracting a desired block of data in response to an address specifying only the center bit of the block. The input address is modified through an arithmetic circuit wherein the address representing the center bit is added to and subtracted from to produce a plurality of addresses which are used to address a plurality of separate memory blocks. The outputs from the memory blocks are passed through a selection alignment matrix circuit which selects from the outp...

A method of operation of a memory array for storage of records of differing predetermined sizes is disclosed which features division of the array into domains which are substantially integral multiples of the predetermined record sizes. In a preferred embodiment the domain allocation may be varied adaptively in accordance with usage so as to enable more fully efficient use of the array.

An arbitration controller providing for equal priority sharing of duplicate copy resources by a duplex plurality of central processing units. Conflicts resulting from simultaneous requests from several CPUs for access to the common resource are resolved at a high rate of speed. In addition, an approximately statistically equal probability is maintained for access of the common resource by all the central processing units.