A method of integrating a chip with a topside active optical chip is described. The topside active optical chip has at least one optical laser device, having an active side including an optically active region, a laser cavity having a height, an optically inactive region, a bonding side opposite the active side, and a device thickness. The method involves bonding the optical chip to the electronic chip; applying a substrate to the active side, the substrate having a substrate thickness over the ...

A semiconductor device including a substantially flat leadframe that includes a die attach area on a surface of the leadframe. A die including solder bumps is placed thereon and a plurality of columns surround at least a portion of the periphery of the die attach area. The die is positioned within the die attach area and the columns have a height substantially equal to the solder bumps and the die on the leadframe.

Submicron-dimensioned, silicon-based MOS-type transistor devices having reduced tendency for "latch up" are formed by removing residual indium dopant utilized for forming a retrograde-shaped indium doping concentration profile of the channel region from the surface and uppermost stratum of the silicon substrate by a rapid thermal annealing process prior to silicon oxide thin gate insulator formation. The inventive methodology substantially eliminates deleterious indium contamination of the gate ...

A p-n tunnel junction between a p-type semiconductor layer and a n-type semiconductor layer provides current injection for an nitride based vertical cavity surface emitting laser or light emitting diode structure. The p-n tunnel junction reduces the number of p-type semiconductor layers in the nitride based semiconductor VCSEL or LED structure which reduces the distributed loss, reduces the threshold current densities, reduces the overall series resistance and improves the structural quality of ...

A semiconductor current limiting device is provided by a two-terminal vertical N(P)-channel MOSFET device having the gate, body, and source terminals tied together as the anode and the drain terminal as the cathode. The doping profile of the body is so tailored with ion implantation that a depletion region pinches off to limit current. The body comprises a shallow implant to form a MOS channel and an additional deep implant through a spacer shielding the channel area. Implanted a higher energies...

A bidirectional optical semiconductor apparatus of the present invention includes: a substrate embedding an optical waveguide, through which output light and input light are propagated; a semiconductor light-emitting device for emitting the output light toward one end of the optical waveguide; an optical branching filter, provided in the optical waveguide, for transmitting at least part of the output light and guiding at least part of the input light to the outside of the optical waveguide; a se...

The invention is a method for constructing an integrated circuit structure and an apparatus produced by the method. The method generally comprises constructing an integrated circuit structure by disposing a layer of doped oxide, the dopant being iso-electronic to silicon, and then reflowing the layer of doped oxide. Thus, the apparatus of the invention is an integrated circuit structure comprising a reflowed layer of doped oxide wherein the dopant is iso-electronic to silicon. In one particular ...

A fluorine-containing organic film having a relative dielectric constant of 4 or less is deposited on a semiconductor substrate using a material gas containing fluorocarbon as a main component in a reactor chamber of a plasma processing apparatus. During the deposition of the fluorine-containing organic film, a scavenger gas for scavenging fluorine constituting the fluorocarbon is mixed in the material gas. The proportion of the mixed scavenger gas in the material gas is changed to adjust the me...

A method of forming a high-k dielectric material which exhibits a substantially lower amount of trap charge within a gate stack region is provided. The method maintains high-temperatures (250.degree. C. or above) such that the substrate wafer is not cooled during the various processing steps. Such a method leads to the formation of a high-k dielectric material which does not exhibit a hysteric behavior in a capacitance-voltage curve as well as an increased mobility on FETs using conventional CMO...

According to one embodiment, a number of trace metal segments or conductors are patterned onto a top surface of a substrate suitable for receiving and housing a semiconductor die. In one embodiment, an insulator layer covers the trace metal segments and separates them from a high permeability core which is mounted on top of the insulator layer. The insulator layer can comprise, for example, solder mask while the high permeability core can comprise, for example, a ferrite rod. In one embodiment, ...