A cycle slip detector interfaces with a phase/frequency detector (PFD), such as might be used in a phase-locked loop circuit (PLL), and indicates when cycle slips occur in the PFD. Typically, the PFD generates output control signals as a function of the phase difference between first and second input signals, with the first input signal usually serving as a reference signal against which the PLL adjusts the second input signal. The PFD provides linear phase comparison between its input signals, ...

Packet buffer equipment in which a buffer and time for packet assembly is utilized for packet header analysis and addition processing to obtain increased efficiency. The equipment aims to receive virtual channel (VC)-multiplexed ATM cells to assemble into a packet on a VC basis maintaining each received cell, to output on a packet basis. As an embodiment, cells are assembled into a packet by storing cells from the top cell to the end cell into a packet buffer memory consisting of a plurality of ...

Antennas with steerable antenna patterns and techniques for using such antennas are described. In accordance with the invention, antenna patterns with one or more NULLs are used. Through the use of digital control signals the antenna pattern is steered so that a source of signal interference, e.g., a multipath signal, will be located in a NULL. In this manner the received signal's S/N ratio can be maximized thereby facilitating demodulation. The techniques of the invention can be applied to tele...

In one embodiment of the invention, a phase selection unit for generating a recovered clock signal (SCLK), a phase select signal generator generates a phase select signals in response to a FWD signal and a BWD signal from a digital filter. The digital filter asserts the FWD signal if the phase of a SDIN (serial digital input) signal leads the phase of the recovered clock signal, and asserts the BWD signal if the phase of the SDIN (serial digital input) signal lags the phase of the recovered cloc...

A signal processor used to process an analog read signal representing data stored on a magnetic disk allows for a faster read operation without requiring an increase in its circuit area or buffer memory space. The signal processor includes a decision feedback equalizer which selectively provides a feedback signal added to a read signal in reproducing data read from a storage medium. The signal processor also performs error correction. In performing error correction, the load of the error correct...

A method for dynamically building a packet processing chain includes providing a plurality of packet processing elements. For each element of a first subset of elements operations indications are provided. For each element of a second subset of elements, expectations indications are provided. Finally, the chain is built by combining elements to form the chain according to a configuration requirement. Elements are selected such that an element's indicated expectations are satisfied by the time it...

A transition between values of two successive bits is detected. The bit after the transition is used as one of the recovered bits. A recovery circuit may independently generate a sampling clock based on an analog signal, and sample the analog signal at time points specified by the sampling clock to generate multiple data bits. A multiplexor is used to provide a bit after the transition instead of a bit generated by the recovery circuit. As all bits after transition are recovered, data encoded in...

A mobile subscriber unit includes a smart antenna having antenna elements for generating a plurality of antenna beams, and adjustable weight control components connected to the antenna elements for selecting any one of the antenna beam. A transceiver is connected to the smart antenna. A beam selector controller is connected to the transceiver and operates in a coarse adjustment mode by jointly adjusting the weight control components when scanning through the antenna beams, and operates in a fine...

Improved phase locked loops are described which handle momentary breaks in an input communication channel. The phase locked loops provide the capability to "hold" the output clock in a communication system at or very near the last output frequency before the loss of input data. Such phase locked loops include a differential phase detector, an electronic selector circuit, and an operational amplifier based loop filter circuit. The electronic selector circuit provides the differential output of th...

A radio receiver includes a plurality of antenna elements for receiving a radio signal from a radio transmitter; a setting part changing an impedance of at least one of the plurality of antenna elements according to an instruction signal; a measuring part measuring a change in throughput in a received signal caused due to the change in the impedance; and an instruction part providing the instruction signal which is changed in response to the measurement result.