The present invention relates to acylated indanyl amines according to the general formula (I) ##STR00001## wherein R.sup.1 R.sup.4 have the meanings given in the description, A is CH.sub.2, CHOH or CH--(C.sub.1 C.sub.3-alkyl), B is CH.sub.2 or CH--(C.sub.1 C.sub.3-alkyl), and R.sup.5 is an aryl or heteroaryl group, possibly substituted by the substituents listed in the description. These compounds are useful in the upregulation of endothelial nitric oxide synthase (eNOS), and may therefore be us...

The present invention relates to test systems for testing integrated circuit devices and to calibration associated systems and methods. One embodiment of the invention provides a method for providing formatted levels for use in a test system. The method includes: providing on a single CMOS IC, a timing generation circuit operative to provide timing information signals; and a formatter in communication with the timing generation circuit.

An enhanced JTAG interface provides an additional clock output at any desired I/O port of a logic device during normal operation. The interface includes a boundary scan data cell associated with each I/O port that enables either input data to the I/O port in a normal mode or routes the boundary scan input data during a JTAG operation. A control cell is associated with each data cell for selectively enabling either a normal mode or a JTAG mode of the boundary scan cell. A set of JTAG instructions...

A latch based random access memory includes an input data register; an input data buffer coupled to the input data register; a latch array coupled to the input data buffer; and a latch array bypass multiplexer for selecting one of the input data buffer and the latch array in response to a memory scan mode signal to generate a first data output of the latch based random access memory from the input data buffer during logic scan testing and a second data output of the latch based random access mem...

A scan-based method for testing delay faults in a circuit comprising controlling a subset of state inputs of the circuit by a skewed-load approach and controlling all inputs other than said subset of state inputs by a broad-side approach.

An integrated circuit device has boundary scan structure coupled between a test input and the test output. The test register structure is used to shift information from the test input to a test output. The test shift register structure contains a data shift part coupled to connections for a functional circuit under test. In parallel with the data shift part is an instruction shift structure. By means of test control signals it is controlled whether instruction information travels from the test i...

A boundary scan tester is provided for testing logic devices. The boundary scan tester includes a boundary scan register, a data decompressor, a data compressor, and a derived boundary scan register. The boundary scan register registers the applied test vectors and test responses of a logic device, and the data decompressor is coupled to an input of the boundary scan register for decompressing the applied compressed test vectors. The data compressor is coupled to an output of the boundary scan r...

An oral hypoglycemic compound for use in the treatment of diabetes mellitus having the general formula ##SPC1## And which is one of the group consisting of: A. the compound wherein R.sub.1 is an aliphatic series containing 2 to 8 carbon atoms; B. the compound wherein R.sub.2 = R.sub.3 and is a member of the group consisting of hydrogen, aliphatic, and aromatic radicals; and C. the compound wherein X represents an amino or a substituted amino radical. The compound is prepared by synthesizing p-am...

The invention concerns a circuit protected against transitory perturbations, comprising a combinatorial logic circuit (10), having at least an output (A); a circuit (20) generating an error control code for said output, and a storage element (24) provided at said output, controlled by the circuit generating a control code to be transparent when the control code is correct, and to maintain its status when the control code is incorrect.

A semiconductor apparatus generates a clock signal used for scan test on an internal circuit of the semiconductor apparatus. The semiconductor apparatus includes a scan chain for performing input and output of data in the internal circuit, a clock generator for generating a launch clock signal for sending data to the internal circuit and a capture clock signal for capturing data from the internal circuit. The launch clock signal and the capture clock signal are generated based on a plurality of ...