A special mode key match comparison module has N-storage elements and a special mode key match comparator. The N-storage elements accumulate a serial data stream, and then determine whether a digital device should operate in a normal user mode, in a public programming mode, or in a particular private test mode. To reduce the possibility of accidentally decoding a false test or programming mode, the data stream has a sufficiently large number of N-bits to substantially reduce the probability of a...

A method and system is provided for creating a tap controller in a slice for use during custom instance creation to avoid the need of a boundary scan synthesis tool. Aspects of the present invention include during slice creation, using a software tool to create a test access port (TAP) from slice resources; during instance creation, allowing a customer to design a custom chip using the software tool to select which structures to use on the slice; and based on the customer selections, reconfiguri...

A circuit and a method of operation thereof are disclosed which provides an enhanced test feature for programmable logic arrays. Programmable logic arrays (PLA's) are becoming more complex and many utilize feedback into the array as part of their normal logic function. Those devices utilizing feedback require an abnormally large number of logic cycles to be run in order to provide a known feedback input into the output circuitry so that the combination of all input signals into the array is know...

Test patterns for testing electrical circuits are generated by a MUX having its output operatively coupled to a Scan-In shift register and inputs receiving seed pattern signals, response signal from a response shift register, positive and negative signals from the Scan-In register. A control logic circuit provides control signals that enable the MUX to select appropriate input signals. The circuit arrangement enables relatively few seed patterns to generate relatively large number of test patter...

A test apparatus according to the present invention includes: a plurality of test modules, connected to either of the plurality of devices under test, for supplying a test signal to the connected device under test; a plurality of control apparatuses for controlling the plurality of test modules, and for testing the plurality of devices under test in parallel; and a connection switching section for switching topology of the plurality of control apparatuses and the plurality of test modules so tha...

In a semiconductor circuit apparatus and its test method according to embodiments of the present invention, the clock enable control circuit can generate in a test mode an enable clock signal by using the substitute enable signal instead of the enable signal output from the enable signal generation combinational circuit and supplies it to the enable input terminal of the sequential circuit. Accordingly, with the simple structure in which the substitute enable signal is used, a proper enable cloc...

Testing combinatorial logic sectioned into macros. The macros perform functions some of which are linear, such as busses, and some of which are non-linear such as PLAs, with the macros being connected so that the total chip can be tested by testing each macro individually to thereby make it unnecessary to model the totality of the macros collectively in terms of primitive logic.

Monolithic structures having high circuit density wherein the circuitry is arranged, and/or includes circuitry, to facilitate testing of said monolithic structure. Method for effectively and efficiently testing the circuits arranged and adapted for testing on a monolithic structure having high density. Namely, a test method for testing logic chips and logic chips adapted to be tested by said test method. A test method is disclosed wherein the logic chip, or monolithic structure, is arranged, or ...

The disclosure relates to LSSD systems for use in digital computers and the like. More particularly, to an organization of logic in such systems to render the clock networks testable with minimal overhead. The advantages of the practice of the invention are particularly apparent and enhanced when the invention is employed in a Level Sensitive Scan Design (LSSD) System generally of the type disclosed in U.S. Pat. No. 3,783,254 and U.S. patent application Ser. No. 701,052, filed June 30, 1976.

A technique of decreasing the number of test patterns required to test a MOSFET module and/or provide the ability to test elements on the module which can not be tested by conventional test techniques. Conventionally, test patterns are applied to the input pins of a MOSFET module and the output monitored at the output pins of the module. Interwoven with the normal test pattern testing is the application of a serial test pattern to selected elements on the module. The serial test pattern is appli...