A circuit for generating a digital output signal from an analog input signal applied to the circuit, including: first and second capacitors; first means including a switching transistor for charging the first and second capacitors whereby the transistor switches the first capacitor out of the first charging means when a voltage across the first capacitor approaches the voltage of the analog input signal; and a comparison means including a comparator having first and second inputs thereto and an ...

A companded stacked DAC is provided which can be used in an A-law or .mu.-law conversion merely by selection. The companded DAC is inherently monotonic and can be integrated with field effect transistors. The current sources of the DAC are switched to only one of two buses. The stacked DAC includes a chord DAC and a step DAC. The two buses which the chord DAC is connected to are maintained at approximately equal voltages by the use of a reference amplifier. The companded DAC uses successive appr...

An MOS, integrated circuit, analog-to-digital converter powered by a single power supply potential and suitable for converting an analog signal equal to that power supply potential is described. The input analog signal is capacitively divided by two; resistor strings interlaced with the resistance ladder of the digital-to-analog converter provides a reduced reference potential. A chopper amplifier is employed in the comparator which includes circuits for reducing offset potentials.

A digital-to-analog converter which is effective for an interpolative decoder for decoding a linear PCM signal is disclosed. An output signal of a binary rate multiplier which develops signals of several less-significant bits of the linear PCM signal onto a time axis is directly applied to a driver circuit, by which is driven the segment of a ladder resistance network corresponding to the least significant bit, the ladder resistance network having segments corresponding to signals of several mor...

A pipelined analog-to-digital (A/D) conversion system enhances the effective data rate of the converter in direct proportion to the number of stages in the pipeline. The pipelined A/D converter operates in conjunction with a charge-coupled device (CCD) multilevel storage (MLS) in a three-bit (eight-level) implementation. Three comparators are used in the three-bit system arranged in a sequential successive approximation configuration with control circuits and a CCD shift register.

A digitally coded output is provided from a sensor, such as an aircraft angle of attack sensor. Groups of unused words from the complete unit distance table are omitted between groups of words that are selected to be used in the code, these unused words being "illegal" words indicating an error if they appear in the output of the sensor. The digitally encoded output of the sensor is, in the preferred embodiment, in unit distance code, and is fed to a programmed ROM where it is converted to binar...

An analog-digital converter supplying a digital output signal in natural or reflected binary code, having an input stage, n consecutive conversion stages comprising two parallel channels of identical structure, in each of which there are two current paths in accordance with the result of a comparison of currents effected in the preceding stage and an output stage to which the switched currents proceed. In the complete converter there are 2.sup.n current paths corresponding to 2.sup.n quantizatio...

A digital-to-analog converter is provided which converts a series of digital binary numbers into an analog signal having an amplitude proportional to the values of the binary numbers. The disclosed embodiment of this invention includes a segment generator having input terminals coupled to receive the most significant digits of the binary numbers to be converted, wherein the segment generator provides a first signal proportional to the values of the most significant digits of the binary numbers. ...

To convert a sample of an amplitude-modulated voltage wave into binary pulses, the sample is simultaneously compared in two coders with two sets of threshold voltages of positive and negative polarity, respectively. Either one of the two coders yields in unbroken succession of pulses, having the same polarity as the sample, whereas the other coder produces a combination of both positive and negative pulses. Following inversion of the pulses issuing from one coder, and upon suppression of the pul...

This is an analogue to digital converter channel including an analogue multiplexer, a switched gain amplifier, a mode amplifier, a sample and hold stage, and an analogue to digital converter. Off-set errors can be precalculated and then corrected for by switching the input to the amplifiers to null, and storing the output from the converter, and the amplified output from the gain amplifier respectively at `X` and `Y` and then combining those stored off-set error signals at an adding circuit at t...