Stages of a graphics data processing pipeline are interconnected by a common bus for conveying data and arbitration signals to and from each stage. Each data transmitting stage arbitrates for and acquires control of the bus when it has output data to transmit to an addressable storage location within a next stage. Each pipeline stage other than a first stage generates a BUSY bit indicating whether it is processing data or awaiting new input data from its preceding stage. When one pipeline stage ...

An interface which connects input/output (I/O) controllers to a data channel in a data processing system. A bidirectional priority bus is provided interconnecting the channel with the controllers. Each controller is assigned a priority level. When a controller requires service, it signals the channel over a common request line and the channel responds with a channel select signal. Each requesting controller gates a binary number corresponding to its priority level onto the common priority bus. C...

A digital communication bus upon which arbitration is distributed in a multiplicity of communicable interconnected bus interface logics supports unique signals to each associated on user device and upon the bus. Arbitration inhibiting signals, called inhibit request signals, allow any one(s) user device(s) to inhibit the new entrance, via requests, into arbitration of all other bus interconnected bus interface logics and associated user devices. Arbitration among bus interface logics already reg...

An interface facilitating data transmission between a control processor, connected to an asynchronous two-way bus, and a plurality of terminals, connected to a common synchronous two-way bus, comprises a microprocessor responsive to periodically recurring access requests from the several terminals. The access requests are short pulses with a recurrence period greatly exceeding their duration, this period being nominally equal for all terminals and sufficient to accommodate one data transfer to o...

A computer system has a plurality of processors sharing a bus. Bus arbitration circuitry is located on each processor for determining bus access. The identity of the processor which is responsible for arbitrating bus access changes from time to time. Each processor has a plurality of possible arbitration states, which are controllable through execution of software by the processor.

An allocation system for the use of a data processing system where plural user systems of the data processing system gain access to parallel busses of the data processing system in a sequential manner based on a priority determination. The priority determination involves an allocation circuit for each user that includes a logic network comprising four bistable flip-flops, an edge triggered D flip-flop and a monostable flip-flop. The flip-flop elements in conjunction with a generated request sign...

This circuitry permits equal access to a shared resource by a number of central processing units (CPUs). In a multiple CPU arrangement, common resource contention problems arise, when several CPUs attempt to access the common resource. To resolve these contention problems, this circuitry is an improvement to arbitration ring circuitry. The circuitry of this invention permits each of the CPUs equal access to the common resource during situations in which each CPU is constantly generating requests...

A data processing system having a main processing unit, a memory subsystem, and a co-processor selectively connectable to said memory subsystem through an Input/Output Channel Controller which includes a control means for arbitrating access to the I/O Bus among the co-processor and the other I/O devices connected to the Bus. Since the co-processor runs programs stored in the memory subsystem, there is a tendency for the co-processor to monopolize the bus with instruction fetch cycles, thereby ex...

A plurality of information handling units communicate asynchronously via a common bus using a single signal line. Each information handling unit includes a self-control type bus utilization unit connected to the signal line and operative to connect the common bus to an internal bus of the information handling unit. This unit includes an own name address generator responsive to a bus request signal for outputting the address of the information handling unit, the address being encoded according to...

Arbitration of a system bus shared by a plurality of digital processors, input and output devices and memories may be shared in an intelligent and efficient manner by using an arbitration method and an arbiter and bus controller circuit which allows a lower priority processor or user to access the system bus during those times in which a higher priority user of the system bus is not actively accessing the system bus. Thus, without altering the priority assignments among multiple users of a syste...