An apparatus including a contact on a substrate, a dielectric material overlying the contact, a phase change element overlying the dielectric material on a substrate, and a heater element disposed in the dielectric material and coupled to the contact and the phase change element, wherein a portion of the dielectric material comprises a thermal conductivity less than silicon dioxide. A method including introducing over a contact formed on a substrate, a dielectric material, a portion of which com...

A semiconductor memory cell and forming method thereof utilizes a vertical select transistor to eliminate the problem of a large cell surface area in memory cells of the related art utilizing phase changes. A memory cell with a smaller surface area than the DRAM device of the related art is achieved by the present invention. Besides low power consumption during read operation, the invention also provides phase change memory having low power consumption even during write operation. Phase change m...

A phase change RAM device, has a first metal wiring for a bit line that is separated from a second metal wiring for applying a supply voltage. A method for fabricating the phase change RAM device includes the steps of forming an isolation layer formed so as to define a T-shaped active area in the semiconductor substrate, forming a word line formed on the active area of the semiconductor substrate including the isolation layer, forming source/drain areas formed at both sides of the word line in t...

Low cross talk resistive cross point memory devices are provided, along with methods of manufacture and use. The memory device comprises a bit formed using a perovskite material interposed at a cross point of an upper electrode and lower electrode. Each bit has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit, decrease the resistivity of the bit, or determine the r...

Briefly, in accordance with an embodiment of the invention, a memory is provided. The memory may include a memory element and a first access device coupled to the memory element, wherein the first access device comprises a first chalcogenide material. The memory may further include a second access device coupled to the first access device, wherein the second access device comprises a second chalcogenide material.

An improved memory device to be used in a D.C. curcuit which device includes a pair of spaced electrodes between which extends a body of a generally amorphous high resistance memory semiconductor material made of a composition of at least two elements and wherein the application to the electrodes of one or more set voltage pulses in excess of a given threshold level produces relatively low resistance filamentous path comprising a deposit of at least one of said elements in a crystalline or relat...

A surface-emitting type device includes a rectification section including a substrate and a first semiconductor layer formed above the substrate, an emission section including a second semiconductor layer of a first conductivity type formed above the rectification section, an active layer formed above the second semiconductor layer and a third semiconductor layer of a second conductivity type formed above the active layer, and a photodetection section including the substrate, a photoabsorption l...

A monolithic memory array including an NPN emitter follower and low threshold amorphous material storage device at each cell without additional cell isolation. An N-type substrate forms a common collector, a plurality of spaced rows of P-type regions form the bases and a plurality of N-type regions form emitters. The amorphous devices are formed over the space between the P-type regions and are longitudinally aligned with a respective emitter and base contact area.

A memory device having a plurality of memory arrays. Each array has a plurality of memory cells, each memory cell including an electrode defining a respective contact area. Each memory array is formed by depositing a continuous chalcogenide layer. This chalcogenide layer, even when continuous, will have active areas formed above the electrodes, and a conductive layer electrically coupling at least a portion of the active areas. The memory array can also include a dielectric volume surrounding at...

A control device matrix comprising: a two dimensional array of conductive elements crossing one another but insulated at a plurality of points, current control device adjacent each of said points and each including electron emitting means disposed between the elements at the points and electrically connected with at least one of the conductive elements thereat and a discrete body of normally insulative switch-forming amorphous semiconductor material at each of said points. Primary circuit means ...