A method for controlling a PWM power stage is based upon dampening current peaks generated by switching of the PWM power stage. The PWM power stage includes at least two MOS transistors of opposite conductivity coupled between an output node of the PWM power stage and respective positive and negative supply lines, and respective free-wheeling diodes. The method includes forming the at least two MOS transistors such that their reverse conduction threshold voltage is smaller than a sum between the...

The present invention provides a system for limiting energy levels across the output of a driver circuitry segment (100). The system provides an output structure (102) adapted to drive an output load (104). A transconductance component (106) is communicatively coupled to the output structure, and adapted to output a transconductance current that is proportional to the voltage across the output structure. A scaling component (108) is communicatively coupled to the output structure, and adapted to...

A novel output buffer circuit including an input circuit, a voltage generating circuit, and an output circuit forms a three-state buffer circuit. The output circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. With such a configuration, a simple circuit using no high voltage insulated transistors and level shift circuits can be made, and the simple circuit can output either a low voltage signal or a high voltage signal responsive to a low voltage...

Long existing performance, noise, and power consumption problems of prior art output drivers are solved by using n-channel transistors as pull up transistors and p-channel transistors as pull down transistors for high performance output drivers. Output drivers of the present invention can be fully compatible with HSTL or SSTL interfaces without using termination resistors. High resolution switching applications are also made possible without consuming much power. Output drivers of the present in...

A driver circuit for driving a load (3) connected between an output (FO) of a first channel driver (D1) and an output (RO) of a second channel driver (D2). The first and second channel drivers (D1, D2) each include switch transistors for charging and discharging the gates of upper and lower output transistors in response to a command from an input pulse, a charging/discharging circuit (A2, B2) for determining a charging/discharging speed, and a detector circuit (A1, B1) for detecting a state of ...

A semiconductor device for driving a load includes a first semiconductor switching element interposed between a power supply terminal and a load, a second semiconductor switching element interposed between the load and a ground terminal, a high-side driver, a low-side driver, and a voltage regulator. The voltage regulator reduces a voltage applied to a control terminal of the second switching element, when a voltage of a load terminal of the second switching element is lower than a predetermined...

A source follower capable of compensating the threshold voltage is provided. The source follower comprises a current source, a switching circuit, and a thin film transistor. The source follower makes the threshold voltage of the thin film transistor constant by using the current source, and makes the input voltage nearly equal to the output voltage by using the storage capacitor and the compensating capacitor. Thus, it can make the error of the output voltage fall in the error range of the gray ...

A driver stage uses a primary driver and a secondary driver to balance drive current when transmitting a new data bit different than bits consecutively transmitted immediately previous to the new data bit. The primary driver activates one of a pull-down device and a pull-up device whenever transmitting a data bit. The secondary driver activates one of its pull-down device and a pull-up device when two or more consecutive are detected to be transmitted. In this case, current flow of the driver st...

Disclosed is an input/output (IO) device for transmitting a data bit signal. In one embodiment, the IO device includes an IO device input node for receiving an input data bit signal, an IO device output node, and a common ground node. The IO device also includes a first driver having first and second n-channel FETs coupled together, first and second p-channel FETs coupled together, a plurality of third n-channel or p-channel FETs each having a drain coupled to the IO device input node, and a plu...

A semiconductor memory device including an array of memory cells. The memory device includes a first output driver coupled to a first output terminal, and a second output driver coupled to a second output terminal. The memory device further includes a voltage divider coupled between the first and second output terminals, to generate a control voltage based on a voltage level present on the first output terminal and a voltage level present on the second output terminal. The memory device further ...