In one embodiment, a clock divider for producing a signal having a fifty percent duty cycle includes signal modifier circuitry connected to provide a variable clock signal. Responsive to first and second control signals of the signal modifier circuitry having respective first values, the signal modifier circuitry modifies a differential clock signal that includes first and second complementary clock signals to produce the variable clock signal, which contains an extended clock phase in every I.s...

A method for dividing a signal having a first frequency by a divide ratio includes selecting, based on the divide ratio, a first pulse width of at least one signal having a second frequency and being generated by at least a corresponding one of a plurality of pulse-width control circuits responsive to at least one signal having a second pulse width. The method includes selecting at least one of the plurality of pulse-width control circuits to be powered-on to generate the at least one signal. Th...

In one embodiment, a ratio clock divider comprises circuitry for producing an input signal from a differential clock signal, part of which includes circuitry for extending a clock phase of the differential clock signal every I.sup.th cycle to produce the input signal, I being an integer. The ratio clock divider also includes circuitry for dividing the frequency of the input signal by I to produce a divided clock signal. The divided clock signal has a frequency that equals the frequency of the di...

A method of designing an electronic circuit system with multiple Field Effect Transistors (FETs) made by a variety of nonstandard industrial processes is presented. With this method, the circuit parameters of the various components of the individual functional building blocks of the circuit system are systematically adjusted to minimize the many deteriorating effects resulting from system-level interactions among these functional building blocks. In one embodiment, the method is applied to a Sil...

A binary frequency divider comprises a plurality of serially connected trigger circuits each comprising a switching means having first, second and third terminals and control means for connecting the first terminal alternately to the second terminal and to the third terminal; first storage means connecting the first terminal to the earth; second storage means connecting the third terminal to the earth, and an amplifier having a negative gain whose absolute value exceeds unity, said amplifier hav...

Frequency divider including three stages each including three transistors, with two being connected in a common emitter circuit, and the third connected as an emitter-follower and providing intra-stage coupling. The three stages are connected in a ring-like configuration providing very high frequency, divide by three operation, and is adapted to be constructed in integrated circuit form. The circuit is suitable for use at low supply voltages.

A clock generator circuit of this invention is for an integrated circuit which is controlled by clock signals obtained by frequency-dividing a standard clock. Three flip-flops, two of which are connected in series, and two logical gates together form a synchronization circuit such that when a command signal is inputted to start testing the integrated circuit, frequency-divided clock signals in synchronism with a standard clock are outputted.

A programmable high-speed frequency divider is provided in which a stage for forming a frequency divider, which is capable of being programmed with a programmable dividing ratio, is simplified in order to reduce the area and circuit complexity. The programmable frequency divider includes a first synchronizing element coupled to an output of a logic detection circuit for generating a synchronized divider output, an additional synchronizing element coupled to the output of the logic detection circ...

Circuitry for locally generating a ratio clock on a chip. The circuitry includes circuitry for generating a global clock signal having a global clock cycle. A state machine includes a counter going through a complete cycle in response to a non-integer number of global clock cycles. The state machine generates a control signal in response to the counter. Staging latches receive the control signal and generate a clock high signal and a clock low signal, the clock high signal and the clock low sign...

A method for locally generating a ratio clock on a chip includes generating a global clock signal having a global clock cycle. A centralized state machine is provided that includes a counter going through a complete cycle in response to a non-integer number of global clock cycles, the centralized state machine generating a control signal in response to the counter. The control signal is provided to staging latches, the staging latches generating a clock high signal and a clock low signal, the cl...