A DC symmetrical FET switch includes second and third switches connecting the well of the symmetrical FET switch to the drains and the source when the symmetrical FET switch is on. When the three FET's are on, the well, source and drain of the symmetric FET switch all exhibit the same input signal, wherein the drains and source to well capacitances are substantially prevented from draining off any of the input signal, thereby increasing the bandwidth and decreasing the insertion loss of the swit...

A power switch, and a method, for use with a power switch having a field-effect transistor (FET) including source, drain and gate terminals. The power switch includes a first field-effect transistor (FET) having a first drain coupled to the drain terminal, a first source coupled to the source terminal, and a first gate; and, a second FET having a second drain coupled to the drain terminal, a second source coupled to the source terminal, and a second gate. The second FET has a gate length (L.sub....

A circuit arrangement with a gate driver circuit for a power transistor is disclosed which is suitable for low voltage applications, permitting a rail-to-rail output without a loss in speed/bandwidth, which is very simple, low cost, low current and area efficient. The gate driver circuit comprises a drain follower with a MOS driver transistor having the gate connected to an interconnection node of a capacitive divider. A first capacitor of the capacitive divider is connected between the drain an...

A switching circuit includes a semiconductor switching element having a control electrode and a source-drain current path, the source-drain current path being connected between a voltage source and a load circuit, a parallel circuit formed by first and second transistors having respective collector-emitter paths connected between the control electrode of the semiconductor switching element and a reference potential point, a first resistor connected to the second transistor in series, a different...

In a conventional semiconductor integrated circuit device, a means for preventing a backflow current has a high on-state resistance, which makes it impossible to reduce the voltage loss in normal operation. A semiconductor integrated circuit device of the invention has a first MOS transistor, a second MOS transistor provided between the first MOS transistor and a power supply terminal, and a means that, in normal operation, keeps the gate of the second MOS transistor at a predetermined potential...

A current regulated circuit arrangement for controlling a power semiconductor transistor, as example a MOSFET or IGBT power transistor, that includes at least two mirror-symmetrically arranged regulated power sources and an output voltage regulator. A first regulated power source is fed from an unregulated power source and controls the gate of the power transistor such that the power transistor is switched into the conductive state. A second regulated power source is fed from an unregulated powe...

A method and an apparatus for implementing a semiconductor switch multi-stage drive circuit. The disclosed method and an apparatus reduce losses in a semiconductor switch when it is turned from an off state to an on state or from an on state to an off state. The reduction in losses is achieved without influencing the dv/dt across the semiconductor switch during a first time period while the semiconductor switch is switching. This reduction in losses is therefore achieved with very little increas...

A technique, for drawing power from the external signal circuit to power on-chip elements for an integrated circuit diode (ICD), utilizes an integrated diode and capacitor. The capacitor is charged by the external applied voltage during the time the ICD blocks the external current flow. The charged capacitor then acts as a battery to power the on-chip circuits to provide active control for the ICD function. This ICD could be provided as a two terminal discrete diode, or integrated onto a larger ...

NMOS composite device Vds bootstrappers that mitigate the effects of decreased power supply rejection and increased channel length modulation in minimum or short channel length devices. The NMOS composite devices have a native or at least a low threshold device over a short channel device, with the gate of the native or low threshold device being controlled responsive to the input or output of the short channel device to clamp the drain--source voltage of the short channel device while holding t...

A switch semiconductor integrated circuit having a switch FET for controlling passage of a high-frequency signal so that the switch FET is switched between on-operation and off-operation. The switch semiconductor integrated circuit includes a logic control section using of an inverter circuit which generates the switching signal in accordance with a control signal applied from outside. The inverter circuit uses a junction-type FET in which the gate of the switch FET is connected to an output end...