A circuit arrangement for generating switch-on signals for driving track-and-hold elements of an analog-to-digital converter operating with interleaved timing comprises a first input for inputting a common reference clock signal, at least one window device for generating clock signals which are interleaved with respect to one another in terms of timing and whose respective time windows in which the respective of the clock signals has a first logic level are derived from the reference clock signa...

A cyclic pipeline analog to digital converter includes a dual mode sample and hold circuit, a multiplying digital to analog converter (MDAC), a sub-analog to digital converter (sub-ADC) and a decoder. The dual mode sample and hold circuit has a charge-redistribution mode and a flip-around mode. The dual mode sample and hold circuit receives first and second input voltages and first and second feedback voltages and generates a differential output signal pair. The MDAC receives the differential ou...

A high speed analog signal sampling system. The system comprises a timing chain having a plurality of delay elements arranged in series and a sample rate multiplier having a delay lock control system responsive to the outputs of first, second and third parallel delay elements in the sample rate multiplier to control the delay of the second parallel delay element so that its strobe signal output occurs one-half the time between the strobe signal outputs of the first parallel delay element and the...

A system for reducing noise coupling in a mixed-signal IC includes a digital clock, an analog clock, and gating signal generator, and a gating circuit. The gating circuit receives a digital clock signal and the gating pulse to generate a gated digital clock signal having no pulses at a sampling edge of the analog clock signal to provide a "quiet time" for analog sampling.

The present invention is intended to realize an analog signal sampling circuit constructed with field-effect transistors wherein errors caused by parasitic capacitance or gate conductance in a switch device is reduced. The sampling circuit of the invention comprises an inverting amplifier, a capacitor, a first switch for selecting a reference voltage Vref or a target signal Vin for input to the capacitor, and a second switch for opening or closing the connection between the input and output of t...

A pulse input apparatus comprises an input circuit for sampling each of input signals for a plurality of channels, an orthogonal memory for storing the sampled signal components of the input signals, sequentially in a direction of its time axis, and a sequencer for reading the sampled data items from the orthogonal memory, in a direction orthogonal to the time axis, to obtain a code representing the time at which the input signal has changed, in accordance with the command read out of a command ...

An apparatus and method for clocking digital and analog circuits on a common substrate is provided. The apparatus and method serves to reduce digitally derived noise at select times during which the analog input signal is sampled. Analog sampling error is thereby reduced while, at the same time, the digital clocking signal maintains maximum frequency. Digitally derived noise is substantially eliminated near the latter portion of each sampling interval to ensure an accurate sampled value exists a...

A high speed analog to digital converter system employs a set of ACT/HACT devices in parallel to buffer a high speed data sampling rate to the processing rate of the analog to digital converters employed. Calibration is maintained by periodic comparison of the results of the same input data.

An electronic sampling circuit for determining redox potentials, and consequently specie concentration, in a photographic solution, applies a linear ramp of a square wave voltage to a first electrode (6) immersed in the solution. The current drawn by an adjacent electrode (12) is converted to a voltage for sampling. A pair of sample-and-hold circuits (40,42) store signals sampled at the peak and adjacent trough respectively of a square wave pulse, and a subsequent analogue difference circuit (44...

A signal processing circuit includes a main input sampling structure with an integrator operational amplifier and input lines including a switched capacitor. The input lines have switched connections to input signal lines and reference signal lines. A replica sampling structure is used in combination with the main input sampling structure to eliminate or reduce signal-dependent current that is drawn from the input signal line and the reference signal line. The replica sampler includes buffered i...