An algorithm and the hardware embodiment for producing a run length limited code useful in magnetic recording channels are described. The system described produces sequences which have a minimum of 1 zero and a maximum of 7 zeros between adjacent 1's. The code is generated by a sequential scheme that map 2 bits of unconstrained into 3 bits of constrained data. The encoder is a finite state machine whose internal state description requires 3 bits. It possesses the attractive feature of reset data...

A length oriented arithmetic decoder constrained to ONE-TO-ONE map in the data string to run length limited string direction and ONTO map in the run length limited to data string direction through an arithmetic encoder preserves the fixed rate of the RLL string and ensures representability. A finite state machine responsive to the arithmetic decoder output provides the trial augends and shift amounts necessary for the magnitude comparison decoding of the data string treated as if it were arithme...

A binary DC balanced code and an encoder circuit for effecting same is described, which translates an 8 bit byte of information into 10 binary digits for transmission over electromagnetic or optical transmission lines subject to timing and low frequency constraints. The significance of this code is that it combines a low circuit count for implementation with excellent performance near the theoretical limits, when measured with the commonly accepted criteria. The 8B/10B coder is partitioned into ...

A systematic method and apparatus for constructing a run length limited code in which the minimum number of continuous bits of the same binary value is constrained to d and the maximum number thereof is constrained to k. In converting m-bit data words to n-bit code words (n>m) to construct the run length limited code, selection means for n-bit code words usable to meet the d, k-constraint and a concatenation rule of the code words selected by the selection means are introduced. The selection ...

A channel coding method for channel-coding digital data includes the steps of (a) inputting 7-bit data, and (b) coding the input 7-bit data into 13-bit channel data with reference to at least one run length limited RLL(2,25) code table, where the minimum run length is 2 and the maximum run length is 25. A channel decoding method for channel-decoding channel-coded digital data includes the steps of (a) inputting 13-bit channel data, and (b) decoding the input 13-bit channel data into the prior-to...

A 16B/18B low disparity code is described. The 16-bit input word is split into two bytes, i.e., into two 8-bit words, and each byte is mapped to a 9-bit word. The image of each input byte under the mapping depends at least in part on its disparity, and also in some cases on the disparity of the other word. Certain of the images under the mapping are then inverted. The decision whether to invert an image depends, at least in part, on the running digital sum (RDS) of the output. The RDS is the sum...

An encoding scheme to translate user information into encoded information, including the steps of receiving the user information and translating the user information into encoded information by employing a new kind of Run Length Limited encoding scheme. The user information and the encoded information have the same cell size.

The invention proposes an apparatus for encoding an information signal. The information signal can be a (d,k) sequence. The apparatus encodes the (d,k) sequence into a (d+n,k+n) sequence by changing the number of zeroes between each time two subsequent ones in the sequence by n. The information signal can also be a RLL sequence of the type (d,k). The apparatus encodes the signal into a RLL sequence of the type (d+n,k+n) by changing the runlengths by n bitcells each.

Disclosed is an error tolerant binary encoded synchronization mark concatenated with a known pattern, such as a VFO pattern, comprising an encoded pattern of a fixed plurality of bits, the encoded synchronization pattern being at maximum Hamming distance from the concatenated known pattern for the number of bits in the fixed plurality of bits. The error tolerant synchronization mark may also be concatenated with the VFO pattern seen in reverse, and the synchronization pattern additionally is at ...

A modulation device and a demodulation device suitably performing DSV control while reducing the size and lowering the price of the hardware. Recording data is modulated at a modulator. In a DSV calculator, the DSV value of a modulated data is calculated in units of 1 DSV frame. A comparator outputs a sign comparison result of a DSV value cumulatively added from the start of recording and a DSV value to a DSV control bit insertion unit. The DSV control bit insertion unit inserts bits of DSV cont...