Read only memory system employing an array of memory elements each of which stores 256 8-bit word segments. Each program word to be read out of the system contains 20 bits. The first 8 bits of a program word are stored in a word segment of a first memory element and the second 8 bits are stored in the corresponding word segment of a second memory element. The last 4 bits are stored in 4 bit positions of the corresponding word segment of a third memory element. The other 4 bit positions of this w...

A preset conductor adapted to receive a preset signal externally or internally applied thereto presets the data control register of a dynamic MOS random access memory having an array of inverting storage cells therein. A MOSFET is connected between a storage node of each of the data control cells and the data control register and a ground conductor. The preset conductor is connected to the gate electrode of each of the preset MOSFETs.

Read only memory system employing four arrays of memory elements, each memory element storing 256 8-bit word segments. Each memory element has address input connections for selectively addressing each word segment and a memory element select connection for enabling the memory element. Each memory element operates in response to a clock pulse at its clock input during a signal at its select connection to read out in parallel the 8 bits of the word segment addressed by signals at the address input...

A decoder for address inputs to a semiconductor memory or the like comprises a NOR gate having a number of parallel input transistors corresponding to the number of address bits to be decoded. The address bits and their complements are selectively connected to the gates of the input transistors and the sources of these transistors, rather than only to the gates as in prior decoders. The layout of this decoder more nearly matches the pitch of rows in a high density dynamic RAM.

A building roof structure designed for efficient drainage of rain. The roof structure consists of a plurality of flat components of simple geometric configuration respectively having outer edges distributed along the peripheral upper edge of the building and being respectively joined one to the next and inclined downwardly and inwardly from their outer edges. These components terminate in inner edges which define a simple polygon and which form the upper edges of a receiving receptacle from whic...

A CMOS precharge and equalization circuit for use with memory cells coupled between paired bit lines in a static random access memory array is constructed without the use of bleeder circuits. The precharge and equalization circuit is formed of a pair of precharge transistors and a pair of equalization transistors for precharging and equalizing the paired bit lines.

A memory system is disclosed which includes input means for receiving a binary word to be stored, in which the word comprises a plurality of bits each having either a "one" state or a "zero" state. Counting means are provided for counting the number of bits in the "one" state and for providing an output control signal whenever the number of such bits exceeds one-half of the number of bits in the word. The output signal of the counting means controls an input complementing gate which receives the...

A static-type semiconductor memory device having a holding-current controlling circuit such that the holding current supplied to an unselected-state memory block or memory chip is greater than the holding current supplied to a selected-state memory block or memory chip. The current supplied to the peripheral circuit for the unselected-state memory block or memory chip is smaller than the current supplied to the peripheral circuit for the selected-state memory block or memory chip, whereby destru...

A content-addressable memory (CAM) has an array of four-transistor memory cells arranged in rows corresponding to stored words and columns corresponding to a selected search word. Complementary column lines couple signals associated with the bits of the search word to the memory cells associated with all of the stored words in parallel. The memory cells of each row are coupled to a common sense line and cause a current to flow on the sense line in response to the search word not matching the dat...

A method for stress testing a memory array in an integrated circuit. Control circuitry selects a plurality of row lines at one time. An overvoltage suitable for stressing the cells of the array is placed on the bit lines. Because a block of cells has been selected, the overvoltage is applied to all cells of the block. The block of cells selected may be either the entire memory array or a portion of the memory array. The selected rows remain selected for the duration of the stress test. Because t...