A shift register has a plurality of stages which output driving signals, each stage including a pull-up transistor to output a first clock signal in response to a logic value of a Q node; a pull-down transistor to supply a voltage from a first voltage supply source to the output in response to a logic value of a Qb node; a Q node controller to control the logic value of the Q node in response to any one of the previous stage's output signal and the next stage's output signal; and a Qb node contr...

An improved dynamic shift register circuit is disclosed. A circuit design is provided to minimize overlapping between two adjacent output pulses in the dynamic shift register circuit. In an application of analog sample-and-hold circuit, the circuit design effectively improves a distortion of sampled data caused by significant overlapping of two adjacent output pulses as control signals.

A bidirectional shift register includes a former stage multiplexer, a latter stage multiplexer, a former stage full-swing shift register, and a latter stage full-swing shift register, all of which have a plurality of registers all of the same type. The former and the latter stage multiplexers output signals according to a forward clock, a backward clock, a forward control signal, and a backward control signal. The former and the latter stage full-swing shift register store the signals output fro...

A shift register circuit including a first shift register unit, a second shift register unit, a third shift register unit, and a fourth shift register unit connected in serial. The second shift register unit includes an output terminal, and a pull down system pulling the voltage of the output terminal of the second shift register unit according to a pull down signal. The fourth shift register unit includes a third switch and a fourth switch. The fourth switch has a control terminal electrically ...

A shift register circuit with high stability includes a plurality of stages, each including a supplementary unit for supplementing an output node with low voltage level. The present invention utilizes an output signal of the output node to feed back to a shift register circuit unit and act as a control signal. The control signal controls the shift register circuit unit, and further the output node of the shift register circuit unit is continuously supplemented with low voltage level. Thus, the s...

In order to improve the reliability of the operation of switching the scan direction in a bidirectional shift register without using a complex circuit configuration or complex timing, a clock signal is maintained at a high level by a controller around the timing of the switching of the scan direction in a bidirectional shift register including a plurality of stages of unit shift registers connected to each other in which the scan direction is switched. Alternatively, a power supply VDD is connec...

Threshold voltage shifts of transistors which are constituents of a bidirectional shift register are reduced to prevent a malfunction in the shift register. A bidirectional unit shift register includes first and second pull-down circuits (41, 42) connected to the gate of a first transistor (Q1) that supplies a first clock signal (CLK) to an output terminal (OUT). The first pull-down circuit (41) includes a first inverter that uses the gate of the first transistor (Q1) as the input node and that ...

A shift register includes multiple stages connected with each other in succession. The shift register stores the threshold voltage of an amorphous silicon thin-film transistor in a capacitor. During operation, the bias applied to the transistor is adjusted according to the threshold voltage stored in the capacitor.

A shift register, a driving circuit and a display device using the same are disclosed. The shift register includes a 1.sup.st and a 2.sup.nd rectifying elements and 1.sup.st.about.4.sup.th transistors. 1.sup.st source/drains of the 1.sup.st.about.3.sup.rd transistors receive a common voltage respectively. The gates of the 1.sup.st and 3.sup.rd transistors and a 2.sup.nd source/drain of the 2.sup.nd transistor are coupled to a 2.sup.nd terminal of the 2.sup.nd rectifying element. The gates of the...

A shift register circuit includes a shift register unit and a buffer. The buffer is coupled to the output terminal of the shift register unit to delay the output signal from the shift register unit. The overlapped voltage of two output signals from two adjacent shift register units can be reduced.