Disclosed herein is a method for fabricating a semiconductor memory device that can prevent oxidation of bit lines when forming an interlayer dielectric for isolating the bit lines. The bit line is formed on a semiconductor substrate where an underlying structure is formed. A silicon on dielectric (SOD) layer is formed on the resulting structure where the bit line is formed. A heat treatment can be performed on the SOD layer with a partial pressure ratio of water vapor (H.sub.2O) to hydrogen (H....

An interconnect structure having improved electromigration (EM) reliability is provided. The inventive interconnect structure avoids a circuit dead opening that is caused by EM failure by incorporating a EM preventing liner at least partially within a metal interconnect. In one embodiment, a "U-shaped" EM preventing liner is provided that abuts a diffusion barrier that separates conductive material from the dielectric material. In another embodiment, a space is located between the "U-shaped" EM ...

Terminating the ends of passive electronic components entails applying a laser-removable coating to one or both of the opposed major surfaces of a substrate. A UV laser beam having a spot size and an energy distribution sufficient to remove the laser-removable coating from multiple selected regions of at least one of the major surfaces to which the laser-removable coating was applied is directed for incidence on the substrate. Relative motion between the UV laser beam and substrate effects remov...

A semiconductor device has a substrate and an electrode layer formed on the substrate, and the electrode layer includes a plurality of conductive layers and an insulating layer which are stacked, the insulating layer being interposed between two of the conductive layers adjacent each other, a through-hole being formed in each of the conductive layers lower than an uppermost conductive layer among the conductive layers, and the through-hole being filled with an insulating material.

A manufacturing method of a multi-layered circuit board allows electronic parts to be mounted adequately and will not hamper performance of the electronic parts. A power terminal (pin) of an electronic part to be mounted on a surface of the multi-layered circuit board is inserted into a plated through hole to connect with a first conductive layer. A detecting section having a detecting hole which is formed coaxially with the through hole and whose diameter is larger than the through hole is prov...

A method for fabricating a single-damascene opening is described. The method includes providing a substrate having a conductive line formed therein. A barrier layer, a dielectric layer, a metal hard mask layer, a silicon oxynitride layer, a bottom antireflection layer and a patterned photoresist layer are sequentially formed on the substrate. The bottom antireflection layer, the silicon oxynitride layer and the metal hard mask layer that are not covered by the patterned photoresist layer are rem...

A method of forming dual interconnects in a magnetoresistive memory cell includes: providing an intermediate product including: a metallization layer including metallic lines; a magnetoresistive junction element conductively connected to a first of the metallic lines by a via through a first non-conductive layer; a metallic hard mask disposed on the magnetoresistive junction element; a second non-conductive layer above the first non-conductive layer in regions over the hard mask and a second of ...

A hardmask layer in the back end of an integrated circuit is formed from TaN having a composition of less than 50% Ta and a resistivity greater than 400 .mu.Ohm-cm, so that it is substantially transparent in the visible and permits visual alignment of upper and lower alignment marks through the hardmask and intervening layer(s) of ILD. A preferred method of formation of the hardmask is by sputter deposition of Ta in an ambient containing N.sub.2 and a flow rate such that (N.sub.2 flow)/(N.sub.2+...

A method for forming a flowable dielectric layer using a barrier layer on sidewalls of patterned flowable dielectrics, thereby preventing a bridge phenomenon between adjacent contact plugs. The method includes steps of: forming patterns on a semiconductor substrate, wherein narrow and deep gaps are formed therebetween; forming a flowable dielectric layer so as to fill the gaps between the patterns; carrying out an annealing process for densifying the flowable dielectric layer and removing moistu...

The invention provides an advanced metallization technique for fabricating a memory cell array on a substrate. The array is fabricated by forming discrete and self-aligned vias in a first layer disposed over the array to form contacts to each of the source and drain junction in the array. Further, self-aligned local area slotted vias are formed in a second layer that is disposed over the first layer to form local area interconnects that electrically shunt all of the source contacts/junctions. Fu...