A method for fabricating a liquid crystal on silicon display device. The method includes providing a substrate, e.g., silicon wafer. The method includes forming a transistor layer overlying the substrate. Preferably, the transistor layer has a plurality of MOS devices therein. The method includes forming an interlayer dielectric layer (e.g., BPSG, FSG) overlying the transistor layer. The method includes planarizing the interlayer dielectric layer and forming a sacrificial layer (e.g., bottom ant...

Before being used for a LPCVD device, a tool is washed first and on the surface of the tool a TEOS-NSG film, which is the film to be formed on a semiconductor substrate and whose etching speed is faster than that of a nitride film, is coated in advance. If the tool coated in the abovementioned manner is used to form a film on the semiconductor substrate, the nitride film formed on the substrate is also adhered to and deposited on the tool and if wet etching is applied to the tool, the TEOS-NSG f...

A semiconductor die and an associated low resistance interconnect located primarily on the bottom surface of such die is disclosed. This arrangement provides a flexible packaging structure permitting easy interconnected with other integrated circuits; in this manner, a number of such circuits can be stacked to create high circuit density multi-chip modules. A process for making the device is further disclosed. To preserve structural integrity of a wafer containing such die during manufacturing, ...

In forming five trenches buried with an intermediate conductive layer for connecting transfer MISFETs and driving MISFETs with vertical MISFETs formed thereover, the second and third trenches, and the first, fourth, and fifth trenches are formed separately by twice etching using first and second photoresist films as a mask. Since all the trenches can be formed at a good accuracy even in a case where the shortest distance between the first trench and the second or third trench, and the shortest d...

A fabrication method for microstructures with high aspect ratios uses a CMOS process to form a desired microstructure on a silicon substrate. The steps of forming a contact plug and a via plug of the process are used to form etching channels in insulation layers, polysilicon layers and metal layers, penetrating to the silicon substrate. An etching process is then performed through the etching channel to form the desired microstructure with high aspect ratio.

A fuel metering apparatus is shown as having a throttle body with an induction passage therethrough and a throttle valve for controlling flow through the induction passage, a fuel-air mixture discharge member is situated generally in the induction passage downstream of the throttle valve, an air passage communicates between a source of air and the fuel-air mixture discharge member, the air passage also includes a flow restrictor therein which provides for sonic flow therethrough, and a fuel mete...

A method of producing a multi-level electronic device that begins with machining into a sheet of dielectric material from a surface to create a set of first indentations at a first level. Conductive material is then deposited into the first indentations to create a set of first conductive features. The first indentations are then substantially filled with dielectric material. The process is continued by machining again into the sheet of dielectric material from a surface and thereby creating a s...

A method of forming an electrically conductive plug includes providing an opening within electrically insulative material over a node location on a substrate. An electrically conductive material is formed within the opening and elevationally over the insulative material. Some of the conductive material is removed effective to recess an outermost surface of the conductive material to from about 100 Angstroms to about 200 Angstroms from an outermost surface of the insulative material after said re...

The invention provides a semiconductor chip manufacturing method, including a step of forming a front-surface-side concave portion in a semiconductor substrate having a front surface and a rear surface, a functional device being formed on the front surface, the front-surface-side concave portion being formed in the front surface and having a predetermined depth smaller than a thickness of the semiconductor substrate; a dummy plug forming step of supplying nonmetallic material into the front-surf...

A multilayer wiring substrate which is high in connection reliability is provided through process steps of forming more than one opening, such as a via-hole in a dielectric layer laminated on a substrate, and then applying uniform copper plating to a surface portion of the dielectric layer including the opening to thereby form a wiring layer. An electroless copper plating solution with at least one of mandelonitrile and triethyltetramine mixed therein is used to perform the intended electroless ...