This invention relates to a system for processing access requests issued from a plurality of access requesting units to a memory. In particular, in a storage system where the buffer storage BS and main storage MS are provided, access is first made to BS based on and access request and if the desired data is not found in BS, access is made to MS. When the desired data is not found in BS and access is then made to MS, acces to BS is carried out based on the next access request from the same access...

A cache memory unit is constructed to have a two-stage pipeline shareable by a plurality of sources which include two independently operated central processing units (CPUs). Apparatus included within the cache memory unit operates to allocate alternate time slots to the two CPUs which offset their operations by a pipeline stage. This permits one pipeline stage of the cache memory unit to perform a directory search for one CPU while the other pipeline stage performs a data buffer read for the oth...

A computing system, having a cache-memory management system, provides selectable access modes for addressable memory, providing cacheable and noncacheable access modes, definable on a fixed page boundary basis. The various access modes can be intermixed on a page by page basis within the translation logic of the cache-memory management system. The cache-memory management system provides high speed virtual to real address translation along with associated system tag data defining access prioritie...

A cache storage apparatus used for a plurality of requestors includes a unit for detecting if consecutive requests by the same requestor have the same access line; a stack unit for storing access addresses to a cache storage unit for each requestor after a cache directory unit was searched; and a plurality of pipe lines allowing the service of plural and concurrent accesses to other than the cache directory unit. In the cache storage apparatus, if there are consecutive accesses to the same line ...

A cache memory capable of concurrently accepting and working on completion of more than one cache access from a plurality of processors connected in parallel. Current accesses to the cache are handled by current-access-completion circuitry which determines whether the current access is capable of immediate completion and either completes the access immediately if so capable or transfers the access to pending-access-completion circuitry if not so capable. The latter circuitry works on completion ...

In an information processing system including a file shared by computer systems each having a central processing system and a main memory, a method for controlling access to the shared file includes a step of storing blocks read from the file into the main memory when the blocks of the file are updated, and a step of comparing at least a portion of the blocks held in a cache memory with at least a portion of the blocks stored in the main memory. When the comparison of at least the portion of the...

A cache for use with input/output devices attached to an input/output bus. Requests for access to system memory by an input/output device pass through the cache. Virtual memory addresses used by the input/output devices are translated into real addresses in the system memory. Virtual memory can be partitioned, with some virtual addresses being mapped to a second memory attached to the input/output bus.

A storage control apparatus contains plural request stacks for storing the access request; a stack selecting circuit for selecting a request stack by accepting the access requests one after another and for storing the access request; and a priority determining circuit for selecting the access request stored in said request stack in order of priority and makes access to a main storage unit in response to an access request from an input-output processor, instruction processor and the like. When me...

A cache memory structure comprises a cache memory that has a plurality of ports for reading data from the cache memory and a plurality of ports for writing data into the cache memory. A switching network matrix having controllable switch elements for connecting of the cache memory ports to bus terminals is arranged between the bus terminals and processors, to an instruction unit of a processor, to a main memory, and to the cache memory. The switch elements of the switching network matrix are con...

A high-speed cache is shared by a plurality of independently-operating data systems in a multi-system data sharing complex. Each data system has access both to the high-speed cache and the lower-speed, secondary storage for obtaining and storing data. Management logic and the high-speed cache assures that a block of data obtained form the cache for entry into the secondary storage will be consistent with the version of the block of data in the shared cache.