A computer system includes a relatively fast, small, random-access memory, and a large, relatively slow, directly-addressable, random-access memory. An address comparator is receptive to the contents of a real address register and has a first output indicating that the desired word is stored in the fast memory, so that the contents of the real address register can be used to address the fast memory. The address comparator has a second output indicating that the desired word is in the large memor...

A system for controlling the transfer of pages between a large disc memory and a much smaller core memory in response to requests for the transfer of pages from the disc memory to the core memory, including a first plurality of control words, which define an In-Core List. Each of these control words is associated with a different core page. The word's fields are used to designate various information related to the disc page located in the core page associated with the word, as well as the availa...

An hydraulic cement composition comprising an aluminous cement and an alum and method of cementing comprising admixing said composition with water and emplacing it in a geologic formation via a well penetrating the formation.

A directory, or index, of variable-sized pages of data for use in a two-level storage system employing virtual addressing, wherein data is stored in a large capacity main storage and retrieved to a smaller, faster buffer storage for processing. If a desired piece of data indicated by a virtual address is not currently resident in buffer storage, the location of the beginning of the page containing that data in main storage is found by searching the directory. Directory addresses for searching th...

A storage device (hereinafter referred to as a high speed store) includes a plurality of registers or locations and has an access speed compatible with that of its processor. Operand and operator entries are entered into one group of said registers in descending and ascending order from opposite ends thereof (a push operation) and removed therefrom (a pop operation) for processing each entry type in a last-in-first-out order. The group of registers is hereinafter referred to as a high speed stac...

A first in-first out buffer memory coupled to a system bus receives all information transferred over the bus. Logic associated with the buffer memory tests if the information received is intended to update main memory or is in response to a cache request. The information is written into cache if the main memory address location is stored in a cache directory. The information received in response to a cache request is stored in a cache data buffer. Other information is discarded.

In a computer system having two levels of memory, a random access memory is used as a slave store for both code and directly addressed data. Each slave store word includes two slave address fields, one for the slave address of an operand and the other for the slave address of the next instruction. Validation means are provided to determine whether the word at such a slave address has been overwritten since the slave address was recorded.

During system initialization, a cache is completely loaded with valid information from main memory. The directory and data buffer are organized in levels of memory locations. Each level of the directory and data buffer is loaded in turn from main memory. Round Robin apparatus, which is preset during system initialization, identifies the next level into which a replacement data word is written on a first in-first out basis. The round robin count for each address location of cache indentifying the...

This invention concerns a method of introducing at least one weft thread into a sheet of warp threads so as to assist in holding the sheet together, the said method comprising employing at least one toothed wheel which is rolled transversely across the sheet periodically to raise and lower predetermined warp threads in a sequence which permits the passage of the weft thread transversely of at least a part of the sheet, and introducing the said weft thread over and under the said predetermined wa...

A cache unit includes a cache store organized into a number of levels to provide a fast access to instructions and data words. Directory circuits, associated with the cache store, contain address information identifying those instructions and data words stored in the cache store. The cache unit has at least one instruction register for storing address and level signals for specifying the location of the next instruction to be fetched and transferred to the processing unit. Replacement circuits a...