This specification relates to performance of partial store operation in a hierarchical memory system which has a buffer store interposed between a processor interrogating the memory system and the main memory of the memory system. Such a partial store operation can be performed on a word of data in the main memory using the buffer store copy of that word of data. The copy of the word of data is read out of the buffer store into a register where it is modified to form a new word by replacing one ...

A so-called "roll mode" technique provides block transfer with a disk-type of direct-access data-storage device (DASD). A set of chained commands for accessing record areas enables rapidly accessing a plurality of records within a given DASD cylinder of tracks. The rotational position of the surfaces is checked. The command within the chain, irrespective of its location, having the closest logical rotational proximity to the instant rotational position of the surfaces is selected as the first co...

An efficient cache write technique useful in digital computer systems wherein it is desired to achieve single cycle cache write access even when the processor cycle time does not allow sufficient time for the cache control to check the cache "tag" for validity and to reflect those results to the processor within the same processor cycle. The novel method and apparatus comprising a two-stage cache access pipeline which embellishes a simple "write-thru with write-allocate" cache write policy.

A processor capable of selecting between a write-back and a write-through mode of operation includes a bus interface unit for transferring information across the external bus. A local cache memory is coupled to the bus interface unit for storing information received from the bus interface unit. The processor also includes a control unit coupled to the cache memory and the bus interface unit. The control unit is operable to restart an interrupted operation from a point of interruption. A storage ...

In a multi-processor unit data processing system, apparatus and method are described for providing that only the most recent version of any data signal group will be available for manipulation by a requesting data processing unit. A "multiple" state for a data signal group is defined by the presence of a particular data signal group stored in the cache memory units of a plurality of data processing units. The "multiple" state is associated with each copy of a data signal group by control signals...

A data processing system includes a processor, a system memory, one or more input/output channel controllers (IOCC), and a system bus connecting the processor, the memory and the IOCCs together for communicating instructions, address and data between the various elements of a system. The IOCC includes a paged cache storage having a number of lines wherein each line of the page may be, for example, 32 bytes. Each page in the cache also has several attribute bits for that page including the so cal...

Disclosed is an electronic exchange with a hot standby memory copy system including main storage devices that are duplexed wherein to improve the processing capacity of a central processing unit and make the best use of the speed of a cache memory, in an information processing apparatus provided with central processing units, main storage devices and cache memories all of which are duplexed, first-in first-out memories that are duplexed and connected to the central processing units, a unit for s...

In a processor module having a local software visible data memory and a write through cache connected to an external memory space external to the processor module over a bus, a method and apparatus for supplementing the local software visible data memory utilizing the write through cache is disclosed which may comprise: a processor bus interface and memory management unit adapted to detect a processor write operation to a preselected location in the external memory space that is not currently a ...

A cached multiprocessor system operated in an ordered pipeline timing sequence in which the time slot for use of the cache is made long enough to permit only one cache access. Further, the time slot for data transfers to and from the processors succeeds the time slot for accessing the cache. The sequence is optimized for transactions that require only one cache access, e.g., read operations that hit the cacgenerally require a second cache access in order to update or allocate the cache. These tr...

A system comprises a first processor having cache memory, a second processor having cache memory and a coherence buffer that can be enabled and disabled by the first processor. The system also comprises a memory subsystem coupled to the first and second processors. For a write transaction originating from the first processor, the first processor enables the second processor's coherence buffer, and information associated with the first processor's write transaction is stored in the second process...