An access unit for a shared memory for use in a microprogrammable processor is provided utilizing a multiplexing scheme. Two functionally different inputs, one for data, the other for microinstructions are exclusively gated to memory in synchronization with microprogram control timing cycles to permit accessing the memory at separate times via a single channel.

A data processing technique is disclosed which permits a plurality of users of a data processing system to share data in a data store, providing independent and asynchronous access to the data for subsequent processing by either user. The sharing of small data items is accomplished without requiring the use of interlocks to prevent one user from obtaining access to the shared data item while the other is processing the data for subsequent replacement in the shared data store. In addition, sharin...

There is provided, in accordance with the present invention, apparatus comprising a shared random access memory in which is stored requests for access to data in a bulk memory unit. The data being stored in redundant storage areas and the requests stored in the RAM include the address of the redundant data. Means are provided for determining if that data request is already in progress through one of the redundant addresses. The first of the addresses accessed causes the others to be blocked to p...

A shared memory computer method and apparatus having a plurality of sources, a memory manager, and memory units in which the memory locations of data items are randomly distributed. The memory manager includes a translation module for locating data items in the memory units and a temporary storage buffer for storing at least a portion of messages between sources and the memory units with respect to data items.

A processor for use in CAT X-ray systems and NMR systems performs floating point arithmetic operations in parallel to shorten processing time. A single program memory and program sequencing unit operates a set of floating point arithmetic units to carry out parallel operations on data set storeed in respective data memories. An integer processor unit executes logical operations and a shared data memory stores constants and other data which is required by the integer processor unit and which is c...

In a data processing system in which a single main memory is shared by two or more basic processing units, each unit is provided with a first buffer address array which stores the addresses of data stored in the associated buffer memory and is searched by this processing unit and with second buffer address arrays which store the copy of the content of the first buffer address array and are searched by the store addresses from the other processing units, so that the information stored in the buff...

A distributed function processing system utilizing a conventional microprocessor operated as a text processor in combination with a plurality of other autonomous processing devices arranged to operate in a coherent processing system. One of the autonomous processors which is a memory control processor serves to periodically overlay a random access accelerator memory with the contents of a main memory system and concurrently resolves conflicts among various other autonomous memory service request...

In a data processing system, data is transferred between a plurality of functional devices through a shared memory without the intervention of the processor. The data transfer is controlled by a Shared Memory Access Channel (SMAC) having a pointer table storing memory addresses to control shared memory accesses and by the functional devices using device addresses, pointer identifers, indicating the pointer to be used from the pointer table, and control codes. The control codes used in the transf...

A digital computer system having a memory system organized into objects for storing items of information and a processor for processing data in response to instructions. An object identifier code is associated with each object. The objects include procedure objects and data objects. The procedure objects contain procedures including the instructions and name tables associated with the procedures. The instructions contain operation codes and names representing data. Each name corresponds to a nam...

A data processor asynchronous demand selector includes a time selector for selecting an asynchronous demand according to the time it is applied to the selector. A spatial selector controls each demand selected by the time selector according to a predetermined, arbitrary criterion. A temporary clock responds to the time selector to derive synchronization signals which are applied to the time and spatial selectors. The temporary clock also supplies synchronization signals having occurrence times d...