While executing program code arranged in nested blocks, a data processing system accumulates words in a stack storage means comprising a pair of registers coupled to an arithmetic unit and supplying thereto operands for processing; a plurality of memory locations in a relatively large-capacity, low-speed memory; and a relatively small-capacity, high-speed memory having a plurality of addressable extension locations. Register means are set to associate the extension locations in one-to-one corres...

The present invention relates to the operational control of a digital computer system which includes the digital logic circuitry for temporarily storing results internal to an execution unit. An input unit of the execution, which inputs operand words to the execution logic of the execution unit, includes a first stack for holding operand words received from an external memory unit and a second stack for holding the result words of the execution logic. The input unit also includes a switch elemen...

Tagged pointer handling apparatus is provided for implementation in a computer system wherein a tag bit is provided for each word in main storage. This invention provides for the mixing of data and pointers within the same storage space, and provides a capability for checking and verifying the validity of the pointers without affecting the performance or operation of other instructions. Only the tag instructions can set the tag bits ON in main storage; all other instructions store data and set t...

The invention relates to data processing systems making use of an addressable memory. It proposes a process and system permitting qualifying terms to be associated with the data contained in the data memory by writing these qualifying terms at locations associated with the data within a qualifier and set aside for this purpose. These qualifying terms are characteristics of the data or the processing undergone by the data. The qualifier memory, which is interfaced with the processor as though it ...

An improvement is disclosed for a computer system wherein a high speed peripheral device sends data words of a first length to a memory which operates with a word of a greater length, for example, twice the data word length. The improvement includes an apparatus for identifying pairs of data words which belong together in a single memory word. Then, a pair of the data words can be written to memory in a single operation, rather than two separate write operations.

A message waiting light control system for use in cooperation with a message storage and retrieval computer includes a microprocessor, a memory, address decoders, and an organization of message waiting lights, relays, and latches. The lights, relays and latches are organized in subgroups as memory mapped input/output words which correspond to the words of bits in the memory. Groups of the latches and relays are addressable. The microprocessor is responsive to an identification code number and a ...

In a data protection apparatus for a multiple CPU system having a common or multiported bulk memory, an interface structure is associated with each of the CPU's. The interface structure cooperates with a firmware engine which is, in turn, a part of the interface control means which controls the transfer of data between the common bulk memory apparatus and each of the several CPU's in the system. Signals generated by the individual CPU's indicative of an emergency situation are applied as input s...

The disclosure relates to a memory mapping system wherein information is stored on a page by page basis in memory in discontiguous locations therein with the address of the next page in which storage is to take place always being available in the controller to minimize delay in storage from the end of one page to the beginning of the following page, regardless of page location in memory. When a user makes a request for storage space in memory, the amount of memory required is determined and the ...

In a data processing system in which the program memory unit and the internal data memory unit are separately addressed, and which special instructions for transferring data between these two units are available, apparatus and method are described for increasing the memory available for the internal data memory unit. The increased storage space takes the form of an auxiliary data memory unit that is activated when the special instruction for the transfer of data signal groups between the program...

An information transferring apparatus comprises a central processing unit, and an input/output unit, a first-in first-out stack having a plurality of memory elements connected in series and being disposed between the central processing unit and the input/output unit, a command register which is set to a predetermined state under program control by the central processing unit, and a control circuit which receives a signal produced from the command register when the command register is set to a pr...