A digital data processor for transferring information with associated devices has an automatically operating executive, i.e. conflict-resolving, logic unit that resolves operating conflicts arising from the asynchronous operations of the processor and the associated devices when one calls for an information transfer with the other. The processor operates under control of the logic unit to store off interrupted status at and load in new status information from memory locations dedicated to this p...

A program controlled computer which comprises independent control circuitry for exchanging data between registers of the computer and the computer memory independently of the execution of program. This arrangement saves computer time as it facilitates the storing and retrieving of data which must be saved during nesting and unnesting of program transfers. For each register that contains data which is to be saved upon the occurrence of a program interrupt, there is provided an auxiliary register ...

A data processing system is described wherein, during linkage to a subroutine, by a single machine instruction, a complete status save and the assignment of a dynamic work area are effected. By another single machine instruction the process is reversed. The elements of the complete machine status and the dynamic work area are retained in a hardware controlled stack, thus permitting nesting of the subroutine calls.

A digital data processing system with a central processor for responding to diverse instructions characterized by having variable length. Each instruction includes an operation code. Certain instructions also include one or more operand specifiers. Each operand specifier can comprise one or more data bytes. Each instruction passes to an instruction buffer. Control circuitry in the central processor decodes the operation code and, in succession, each operand specifier byte. The operand specifiers...

A microprocessor system working in conjunction with an application dependent logic module tailored to serve the particular requirements of a given peripheral device. A microprocessor of a uniform architecture works in conjunction with all types of application dependent logic modules to provide instructions and control for data transfer operations. Means are provided in the microprocessor for operation in a normal mode whereby a first set of accumulator registers and flag registers are used exclu...

A mechanism, including a memory, sequences operation in a controlled processor. Each operation is stored in memory together with a portion indicating the current state of predecessor operations required to be completed before execution of the current operation. Also associated with the current operation is provision for at least one address of a successor operation. A predecessor portion is updated as the predecessor operations are performed and at a predetermined state, the current operation is...

A mixed hardware register and memory architecture is provided by the present invention to maintain the advantage of variable length stack frames while eliminating the requirement for a stack pointer. The invention includes a global register bank and a stack register bank with two independent address means for addressing the global and stack register banks. Registers are provided as temporary memories for the source operand and destination operand, and a second data path is provided for transfer ...

In a computer system of a microprogram control type which processes a succession of instructions to produce a succession of store data units and a succession of store requests under control by a microprogram controller, the store data units being written into a memory by control of a memory controller according to the store requests, a specific one of the instructions being retried from a checkpoint on occurrence of an error during current processing of the specific instruction, the microprogram...

A data shunting and recovering device is provided to shunt and hold the data stored in a register and its address before writing the register during a delay period following generation of an interrupt. This data is then restored into the register when an instruction of recovering is given. Therefore, it is allowed to achieve the moderating effects of delaying the stopping of the stage advance in data processing upon generation of an instruction for interruption without loss of data stored in the...

An improved system for saving state during a call operation and restoring state during a return operation in a computer system in which different call and return operations require the saving and restoring of different amounts of state. The components of the system are call instructions whose operation codes specify the amount of state to be saved, frames which contain either basic state saved on every call operation and restored on every return operation or basic state and extended state saved ...