A microprocessor comprising: an address data path; an arithmetic logic unit data path, said data paths being capable of simultaneous operation; an information bus; a shared bus register; a shared input multiplexing apparatus for selectively transferring address and data information from said information bus and data information from said arithmetic logic unit data path to said shared bus register; and a multiplexing apparatus for transferring information from said shared bus register to said ari...

A single-chip microprocessor device of the MOS/LSI type contains an ALU, several internal busses, a number of address/data registers, and an instruction register (IR) with associated control decode or microcontrol generator circuitry. The device communicates with external memory and peripherals by a bidirectional multiplexed address/data bus and a number of control lines. In addition to the main off-chip memory, a smaller on-chip memory (including both ROM and RAM) is provided which allows execu...

A microcomputer system having a central processing unit (CPU) responsive to mode control signals for operating the system in respective operating modes, a power supply circuit for supplying a reset signal to the CPU, a memory, and a keyboard, is provided with a mode selecting circuit which includes a logical gate with inputs and with outputs coupled to the CPU for supplying the mode control signals, a selector switch device connected with the logical gate for selectively determining which of the...

A programmable data path device capable of operating as a general purpose hardware accelerator. The device includes a plurality of processing cells, memory such as RAM or EPROM for storing data path control words, and an address module for sequentially providing data path control words to the processing cells. Each cell includes an ALU, a multiplexer and a register. For each cell, in response to the data path control word, the multiplexer selectively couples the contents of one register to one o...

A parallel processing computer comprises at least a memory for storing program as well as data and instructions for executing the program, a plurality of functional units, a node driving register for indicating executable instructions which are allowed to be executed by the functional units, and a mode register giving information to the functional unit as to whether the processing to be executed is of serial nature or parallel nature.

A computer system has a system bus with several sockets or slots therein which receive memory modules. Each module can be used to implement at least one of a variety of functions. The functions include operating system programs, application programs, and random access memories (RAM). Each slot has a module select line coupled to it at the same location. A module select circuit is provided which enables the module select lines to select the appropriate module or modules. Modules implementing the ...

A hardware controlled pipelined processor having an interpretive storage and multiple execution units employs interpretive storage "milli-instructions" and an interpretive execution "milli-mode". Additional hardware controlled instructions that are exclusively used in milli-mode may be added to provide additional controls or to improve performance (they augment the architected instruction set). Milli-mode routines intermingle milli-mode only instructions with architected instructions to implemen...

A system, apparatus and a method for implementing multifunctional memories is disclosed. The multifunctional memories perform a variety of functions during execution of extended instructions in a reconfigurable data path processor composed of processing nodes. In one embodiment, a processing node can be comprised of modular processing elements to perform computations associated with an extended instruction. Also, such a node includes at least two multifunctional memories and a data flow director...

In a dynamically compiling computer system, a system and method for efficiently transferring control from execution of an instruction in a first representation to a second representation of the instruction is disclosed. The system and method include the setting of a tag for entry points of each instruction in a first representation that has been translated to a second representation. The tag is stored in memory in association with each such instruction. When a given instruction in a first repres...

Disclosed are a single-chip micro-computer optimized for an electronic memorandum book, an electronic dictionary or the like by suppressing the increase of the number of terminals, and an electronic apparatus having therein the single-chip micro-computer. The single-chip micro-computer has: a mode setting register for establishing a mode setting signal for either a first mode for outputting a memory address signal or a second mode for outputting an arithmetic operation output stored in an output...