A peripheral unit for a microprocessor system connected to a microprocessor comprises means for selecting whether an operation of the peripheral unit is to be halted in response to an inputted signal, and means for prohibiting the supply of a signal for activating the peripheral unit in response to the output of the selecting means. The peripheral unit, further, comprises means for canceling the operation of the prohibiting means to supply the signal for activating the peripheral unit in respons...

A calculator having constant memory utilizing a classical CMOS metal gate process, a low power microcomputer with on-chip and external constant memory capability. Incorporation of a switched negative voltage and a non-switched negative voltage to the appropriate P (-) wells enables the power hungry clocked logic to be turned off while power is maintained on the internal static RAM, on the digit latches, and on the R-lines which connect to both the internal and external RAM. Thus, semi-non-volati...

A microcomputer having an instruction memory is provided with a high-speed sense amplifier which can selectively operate in either of a high-speed operation mode or a low-speed operation mode. The high-speed sense amplifier is activated full time or at a large duty rate in the high-speed operation mode and is activated at a low-duty rate in the low-speed operation mode. By operating at a low-duty rate in the low-speed mode, a considerable power savings is realized while retaining the high speed ...

In response to a software instruction, a static microprocessor is placed in a low current mode by disabling clock pulse generation. Means are provided for disabling a master oscillator when a STOP instruction is decoded. Additional means are provided for inhibiting clock pulses when a WAIT instruction is decoded without disabling the master oscillator. Clock pulse generation is again enabled upon receipt of a reset or interrupt signal.

A peripheral control processor for controlling data communication between a host processor and a peripheral unit in response to command signals applied to the host processor. The peripheral control processor has an idle time or a standby condition when data communication is not required. When the peripheral control processor is idle or in a standby condition, a control circuit, within the processor inhibits a control clock signal which activates transistor elements of an internal circuit in the ...

In response to a software instruction, a static microprocessor is placed in a low current mode by disabling clock pulse generation. Means are provided for disabling a master oscillator when a STOP instruction is decoded. Additional means are provided for inhibiting clock pulses when a WAIT instruction is decoded without disabling the master oscillator. Clock pulse generation is again enabled upon receipt of a reset or interrupt signal.

A method and apparatus for reducing power consumption in a data processing system by interrupting the supply of clocking pulses to selected portions of the system in response to a power-down signal provided by a data processing portion of the system only if the state of a respective control signal indicates that that particular portion of the system is then disabled or otherwise inhibited from interrupting the operation of the data processing portion.

A real-time power conservation apparatus and method for portable computers employs a monitor to determine whether a CPU may rest based upon a real-time sampling of the CPU activity level and to activate a hardware selector to carry out the monitor's determination. If the monitor determines the CPU may rest, the hardware selector reduces CPU clock time; if the CPU is to be active, the hardware selector returns the CPU to its previous high speed clock level. Switching back into full operation from...

Novel techniques for controlling a processor's clock frequency and/or fan so as to prevent overheating are disclosed. The invention attempts to maximize the processing speed of the processor while preventing overheating or to reduce power consumption. In a preferred embodiment, the invention monitors a processor's activity and its temperature. When there is no activity for the processor, a slowed clock frequency is used, thereby saving power and lowering the thermal heat produced by the processo...

A pipeline processing apparatus having reduced power consumption including a plurality of serially connected stages, a plurality of clock signals different in phase from each other supplied to the stages individually. The clock signals can be stopped independently, so as to limit power consumption.