A repeat is performed in a computer system after detection of an error in the operation, the circumstances then being changed as much as possible. The clock frequency is then decreased by the selective blocking of a part of the clock pulses, so that second clock pulse cycles are produced which are composed of the same but wider spaced clock pulses. All functions remain possible duringthe second clock pulse cycles, be it at a lower speed. The circumstances can be further modified yet by first com...

The recovery of a signal on a common bus in a data processing system in which contiguous bus cycles may be generated for the transfer of information between any units coupled to such bus by a method and apparatus which enables such recovery to take place during a first or just completed bus cycle. The following bus cycle takes advantage of an arrangement by which the signal may not be stable until a predetermined point in time in each bus cycle. Data, address and control signals may be recovered...

A radiation hardened register file renders a central processing unit intrinsically hard to the disruptive effects of nuclear radiation by providing means for establishing a valid rollback point for each computer instruction operation performed in the central processing unit. Dual data register images provide alternate locations for storing data operands in the register file. A pointer register stores a signal the truth state of which indicates which of the two images currently provides the prope...

A data processor has provision for error recovery by the division of a program into a set of program blocks. The apparatus has a main store and a cache store that preserves the states that have previously been taken up by items of information prior to commencing each block so that the states of the items of information prevailing at the beginning of a block can be restored if required.

A maintenance arrangement responds to a false signal condition, produced by a data handling system, by recycling the timing generator controlling the data handling system to cause the signals in question to be repeated. In order to determine whether the false signal condition occurred only momentarily or remains present during the recycle operation, two types of detecting circuits are provided. Error detecting circuits respond if the false signal condition has a single occurrence, and does not r...

A register device includes a register set group, a switching control unit, a write control unit, a write flag memory unit, and a read control unit. The register set group consists of a plurality of register sets each constituted by a plurality of registers. The switching control unit selects a register set to be used in processing from the register set group in response to a saving/recovery instruction. The write control unit writes data in registers of the register set selected by the switching...

In a multiprocessor system, an error occurring in any one of the CPUs may have an impact upon the operation of the remaining CPUs, and therefore these errors must be handled quickly. The errors are grouped into two categories: synchronous errors (those that must be corrected immediately to allow continued processing of the current instruction); and asynchronous errors (those errors that do not affect execution of the current instruction and may be handled upon completing execution of the current...

When control of a control program stored in a memory of a microcomputer runs wild and enters an otherwise unused memory location, an instruction written in the otherwise unused location returns the control to its start state.

A restart circuit for a digital processor is disclosed. A regularly serviced processor signal is continuously monitored and if an intermittant soft failure of the processor occurs, causing the processor signal to go high or low or toggle in an irregular fashion, a restart pulse is automatically generated. Thus, with the occurrence of a soft failure, the operator no longer has to manually reset the processor system.

A data processing system handles memory management exceptions caused by a faulting vector instruction in a vector processor by halting the execution of the faulting vector instruction being executed when the exception occurred and by setting the state information for the vector processor to acknowledge the presence of the exception and to include information about the suboperation of the vector instruction being executed when the exception occurred. The scalar processor is not interrupted at thi...