Binary logic is added to the binary logic normally utilized for the purpose of generating and decoding binary code combinations which reflect the order of use of a number of units, utilized in sequence, to thereby indicate the unit least recently used (LRU). Disclosed is the utilization of six binary bits which are updated in accordance with a sequence of use of four units to thereby indicate the least recently used one of the four units. In accordance with known LRU techniques, there are 24 val...

Circuitry is disclosed for detecting malfunctions in a communication system having duplicate central data processors, only one of which may be active at any given time. The circuitry detects malfunctions during the execution of operational programs and classifies the malfunctions as to whether they are caused in the Central Processor, Instruction Storage, Process Storage, or Peripheral Units. The circuitry includes a Match Network for matching signals between duplicate copies of the central proc...

The invention provides arrangements for diagnosing faulty equipment using background job diagnostic software running in the on-line PP250 system. Each processor is provided with a diagnostic interface which is connectable to a processor-store bus, either directly or by way of a multiplexor, and which is addressable as part of the PP250 memory complex. Each diagnostic interface provides facilities for (i) forcing data patterns into the microbits and the data area (highway HO), (ii) monitoring imp...

A test facility which utilizes a digital computer to control and analyze the results of tests on equipment which is remotely positioned from the computer is disclosed. The equipment to be tested is interfaced with a simple portable test set which is positioned at the equipment to be tested. The computer and the portable data set are interfaced with a conventional telephone network. Digital data words specifying the test to be performed are transferred from the computer to the portable test set v...

A computer controlled circuit tester is provided for applying predetermined signals to, or taking signals from, individual ones of an array of pins to which the circuit to be tested is connected. Identifier characters are decoded to determine tests to be performed in accordance with associated data characters. Provision is made for blocks of pins making up the array to be successively addressed automatically for energisation according to the data characters and also, using a particular identifie...

Diagnostic testing of a central processor is provided in conjunction with a memory coupled with the processor without any requirement for an input device such as a tape or card reader. Local storage of a test program is provided in the processor which, under the control of a local control store, enables the transfer of the test program to the memory for execution. The central processor may thus be given an initial test to insure a basic performance level.

An input/output processing system comprises a number of modules including at least a pair of processing units connected to operate as a logical pair and a system interface unit having a number of ports. Each port connects to a different one of the modules for interconnecting pairs of modules for communication over a number of switching circuit networks included in the system interface unit. The system interface unit further includes control logic circuits for disconnecting each processor of the ...

A fault interrupt system is arranged, upon the detection of a fault to cause a processor in which the fault is detected to enter a fault check-out routine. Successive fault conditions detected while performing the fault check-out routine causes re-entry into that routine. A faulty processor is therefore, trapped within the fault check-out routine. Additionally the detection of a fault causes the master capability register of the fault detecting processor to be overwritten with a capability defin...

An electronic scanner is started by a central processor to asynchronously scan a number of lines. When the scanner detects a calling line, it stops and calls the processor. The processor then starts the scanner again to operate till it detects another calling line or reaches the last line to be scanned. It is possible with such a system that the scanner will not operate properly and the central processor will not be informed of this fact. The invention provides for check scanning, without event ...

Periodically operating test microprograms and fault detection circuits for a data processing system containing a microprogrammable control memory are disclosed. Said fault detection is performed concurrently with normal data processing in a time-shared fashion. Also disclosed are means for storing fault information and the status of said system at the time of fault detection, and a terminal coupled to the system by communication lines for enabling the execution of software diagnostics and the re...