The disclosure relates to a multiprocessing system which may be reconfigured in a controlled manner to redesignate the functions assigned to particular similar units so as to provide continuous data processing capabilities. In certain circumstances, a failed unit or group of such units can be isolated from the system. Whenever a malfunction is sensed which requires corrective measures, the system operation is halted, the different operational units of each of the processing groups which make up ...

A circuit arrangement for detecting and isolating malfunctioning system units of a program controlled data processing system, wherein the system units are processing units and storage units. The system units are duplicated for increasing operational reliability. In the processing system constituting triplicated and/or duplicated system units each of the processing units is connected to the storage units through triple standard connections. A combination of a comparator and a majority logic circu...

An array of processing element nodes are provided on a semiconductor wafer. A mixed redundancy approach is preferably employed wherein two spare core logic circuit modules 52, 58 are available for use at each node. Each spare core logic module can be connected to one of four different nodes. An H-net 94 interconnects adjacent nodes in such manner that faults in the circuit modules can be easily tested and repaired.

The present invention is concerned with a method of deselecting the features of a xerographic printing machine to be able to continue operation of the machine even though a fault has been detected. In particular, the control isolates a detected malfunction to a particular input or output, determines that the particular input or output is related to a specific machine feature that has been selected for a particular job requirement, and instructs the operator by message to deselect that particular...

An array reconfiguration apparatus is employed in large integrated circuits and large systems. The apparatus makes use of spare wires and/or computation elements which are incorporated in the array. The apparatus uses spare wires in place of defective wires and/or the apparatus uses spare computation elements in place of defective computation elements so that an operational system may be created in spite of the occurrence of numerous manufacturing or lifetime faults. The excess wires are utilize...

A multiprocessor system includes a segmentable parallel bus for dividing the multiprocessor system into several independent groups of processors. Each group of processors can access its segment of the segmentable parallel bus to carry on processing within the group simultaneously and independently of processing occurring in another group of processors on another segment of the segmentable bus. The multiprocessor system of this invention further has the capability to reconfigure the segments and ...

A computer system in a fault-tolerant configuration employs three identical CPUs executing the same instruction stream, with two identical, self-checking memory modules storing duplicates of the same data. Memory references by the three CPUs are made by three separate busses connected to three separate ports of each of the two memory modules. The three CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the functi...

A document processing apparatus that utilizes a plurality of resources, such as CRT displays and printers, are provided. A control system can determine if a resource has a fault and can select an alternative resource if it is capable of providing a functional output to the user. The control system can further determine if a resource is faulty but will not interfere with the data processing and can accordingly continue the operation of the document processing apparatus.

A number of intelligent nodes (bus interface units-BIUs and memory control units-MCUs) are provided in a matrix composed of processor buses (105) with corresponding error-reporting and control lines (106); and memory buses (107) with corresponding error-reporting and control lines (108). Error-detection mechanisms deal with information flow occuring across area boundaries. Each node (100, 101, 102, 103) has means for logging errors and reporting errors on the error report lines (106, 108). If an...

A fault tolerant interface station for processing and transmitting data, comprising first, second, third and fourth interface units. Each of the first and second interface units includes a receiver to receive input data, first and second memory sections, data lines to transmit data between the receiver and the first and second memory sections, and a controller to control the transmission of data between the receiver and the first and second memory sections. Each of the third and fourth interface...