In an electronic computer system wherein, when a microprogram-controlled central processing unit receives a stop signal from a console, the contents of a group of registers are assigned to predetermined fixed areas in a main memory and, in response to a start signal, the assigned contents of the group of registers are delivered from the fixed areas to the group of registers. The reading and writing of the contents of the group of registers within the central processing unit is effected for the f...

A data processing system incorporates diagnostic apparatus which enables service personnel to specify the type of instruction which will cause the system to halt when it starts processing that instruction. The diagnostic apparatus includes a plurality of switches which are used to set up the bit pattern of an instruction op-code specifying the type of instruction to be tested. This bit pattern is applied to a comparison circuit included within the diagnostic apparatus which compares the bit patt...

A data processing system comprises a data processing unit coupled to a cache unit which couples to a main store. The cache unit includes a cache store organized into a plurality of levels, each for storing a number of blocks of information in the form of data and instructions. Directories associated with the cache store contain addresses and level control information for indicating which blocks of information reside in the cache store. The cache unit further includes control apparatus and a tran...

A relational break signal generating device including two relational comparators which independently compare an address input from a microprocessor to reference addresses previously input thereto and generate output signals which are fed into a combinational logic circuit that produces false and break signals when a prespecified relationship between the input program address and the two reference addresses occurs. The device also includes a circuit for generating pulses each time a break point i...

A control system for a plurality of I/O apparatuses used for transferring data between a main memory and an I/O apparatus controlling device through a channel control device. If an error occurs in the data transfer, no response signal is sent to the I/O apparatus controlling device from the channel control device and the absence of the response signal is detected by time supervision in the supervising circuit in the I/O apparatus controlling device, so that only the portion of the I/O apparatus ...

A personal computer/electronic typesetter interface includes an expansion board suitable for insertion into each of a plurality of personal computers functioning as page composition work stations, wherein one or more of the work stations is also connected for communication to an electronic typesetting machine. The expansion board includes logic for converting the data obtained in a preselected file from the coded format generated by the page composition work station to a second coded format reco...

A data processing system comprising an instruction control unit for controlling system operation, a storage control unit for storing data used for the system operation, and a machine check interruption portion for carrying out a machine check interruption when an error occurs during the system operation. The instruction control unit has a system control register group for storing system control data. The storage control unit has a copy register group for storing data copied from the system contr...

A system for processing machine check interruption using a data processor which outputs a machine check interruption signal by detecting the generation of a machine check condition and which performs interruption processing on the basis of the machine check interruption signal. The data processor includes a specific code detector which detects a specific interruption signal among the machine check interruption signals, a signal converting circuit for converting the machine check interruption sig...

In a method of controlling a multicomputer system which includes a plurality of computers connected to a common transfer bus, each of the plurality of computers decides whether or not the adjacent computer is abnormal, and the computer which has decided that the adjacent computer is abnormal cuts off this adjacent computer from the transfer bus.

An address recall system coupled to a processor to permit operator examination of a predetermined number of executed system addresses. A processor system address is manually inserted to the recall system. When a system address being executed compares with the operator address setting, an address equality signal is generated. The recall system logic generates either a stop or interrupt state for the processor responsive to actuation of another manually operated input switch. Addresses being execu...