A remote test and control system for use with a data communications network having primary and backup facilities provides full network testing and switching capability from a central location, thereby obviating the need for manual supervision at the remote data terminal stations served by the network.

A communications exchange for automatically interconnecting subscriber lines and trunks employs a switching network operable to establish a large number of possible message transmission paths between subscriber terminators and trunk terminators; multiple computers are operable simultaneously upon network transmitted message processing data to similarly process the data and produce output signals; and communication of data between the switching network and computers is established through a syste...

A microprogrammable data communications preprocessor exercises detailed control over a multiplicity of data lines communicating with a microprogrammable central processor while requiring central processor attention on a message basis only. Further minimization of central processor intervention is achieved through a direct memory access channel which permits data transfer directly from the preprocessor to the main memory of the central processor. The preprocessor also includes a line adapter asso...

This disclosure relates to a multiprocessing system having a plurality of different units such as processor, I/O units and so forth that can be arranged into individual processing groups, the functions of which units can be redesignated in order to maintain continuous operation of the system should a malfunction occur in any one or more of such units. Each processing group is provided with a redesignator unit to represent that group, which redesignator unit senses malfunctions in any of the unit...

An automatic fault detection and modem bypass circuit for a standard land line data transmission system containing a plurality of series connected modems arranged in a conventional hub configuration is disclosed. A relay is located in a central collecting station of the hub and connected so as to open an input line to at least one of the modems and an output line from a line amplifier connected to an output line of the same one of the modems upon the occurrence of a fault in the input line to su...

A large number (e.g., 20 or more) independent processors are connected by a network that provides high data throughput (e.g., 64 megabits/second). The network has redundant data, arbitration, and status/control buses. The buses extend across a plurality of microstripline backplanes connected together by impedance-matched twisted-pair cables. Data is transmitted in packets, along with status signals that provide error detection information.

A method of operating a communication system which includes a number of host systems each communicating via sessions with other devices over different connections and in which the sessions assigned to a failed connection are suspended for a first and second time period and non-destructively moved to an alternate connection when a unique command is issued by one of the host systems and received by a control unit involved in the failed connection.

A distributed, fault-tolerant, self-repairable, reconfigurable signal processing system with redundant elements comprising signal processors, mass memories and input-output controllers interconnected by redundant busses forming a high reliability system. The input-output controller element has redundant busses for interconnecting multiple fault-tolerant distributed signal processing systems into a network configuration. One signal processor element in a system is initially designated as the exec...

A ring communications system having a double ring format where the integrity of both rings is continuously checked, and where repair of the network is automatically accomplished upon the detection of the return to operation of a defective ring.

A hardware and algorithm synchronizing arrangement comprising a subsystem synchronization interface circuit is disclosed for controlling the testing of multiple interconnected processors. The circuit permits the pausing of one processor to cause the other interconnected processors to pause as well. The circuit enables a synchronized resumption of the interconnected processors operations. Logic circuitry and signaling interconnections control individual and multiple simultaneous pauses and full d...