A testing circuit for determining the probability of a cross-coupled flip-flop existing in a balanced state within a predetermined input timing range as the result of critically timed input signals. One of the inputs of the flip-flop under test has applied thereto periodic input signals while the other input has applied input signals the timing of which is caused to vary around the timing of the other input signals. Within this latter timing range, at the perfect "race" point, i.e., when both in...

A portable circuit tester is disclosed which features efficient and simplified testing and fault identification of electronic units, such as circuit cards or the like. The tester incorporates an executive test program stored in a programmable read-only Memory (PROM) and accepts programmable test information related to individual units under test from PROM cards. The combination of the executive test program and a PROM card automatically applies test patterns to the unit under test and which patt...

A monitoring circuit for digital circuits is disclosed. The monitor is primarily applicable to digital circuits which operate in a cyclic mode with the digital patterns generated during each cycle being repeated in a predictable manner. A predetermined number of expected bit patterns are stored in a programmable memory. The stored bit patterns correspond on a bit-by-bit basis to the bit patterns generated by the circuit being monitored when this circuit is operating normally. In the self-scan mo...

A battery operated microcomputer controlled programmable circuit testing device. Standard I/O/memory devices (25a, 25b) are connected to a microcomputer (20) in such a manner as to treat the I/O ports (46, 47) of the I/O memory devices as programmable interfaces and to allow pin receptors in a socket (10) to be individually programmed as inputs or outputs. Double detent switches (12, 13) connected to testable inputs T0, T1, 45) the microcomputer are used to scroll a roll table containing names o...

A word recognizer probe to be removably incorporated with the mainframe of a logic analyzer is disclosed. The use of serial input-parallel output type memory means in the probe minimizes the number of interconnection signal paths between the probe and the mainframe regardless of the input bits to be recognized.

An electronic tester for testing an electronic structure having high circuit density, such as large scale integrated devices, system, and subsystem structures having a plurality of interconnected large scale integrated devices, and the like. The tester utilizes m words each containing n binary bits, where m is any integer in the range of one hundred through multiple thousands and n is any integer in the range of one hundred through multiple hundreds. The n binary bits of each word are respective...

One known technique for testing a digital logic circuit assembly counts the logic level transitions at output and/or test point terminals while exercising the assembly with a fixed set of Gray code related input voltages. Many faulty assemblies are detected by the production of unexpected counts. The present disclosure teaches the addition of ONEs counting to improve the rate at which faulty assemblies are detected.

A test circuit for logic circuits of the present invention is constructed with a register for storing data to be operated in the logic circuits and its operation results and interface circuit is connected to the register through an internal bus and is controlled from external terminals. The data to be operated on by the logic circuits is set in the register directly from the interface circuit for operation, and the operation result data stored in the register are outputted to the external source...

A technique of testing a MOSFET planar board in which each of the chips on the planar board can be electronically isolated for individual testing. In MOSFET technology there are two off chip inverters between the output logic blocks and the pins. These are the preoff chip inverter and the off chip inverter. A NOR gate is formed by adding an additional input line to each of the preoff chip inverters of each of the chips on the board, and the output of each of the chips which are not to be tested ...

Apparatus as disclosed which comprises a register normally operable in the parallel data in/parallel data out mode but which has control mechanisms for allowing it to be converted to a serial data in/serial data out register. This register comprises part of a register based state machine. When the register is locked in a given mode so that a predefined control bit pattern is maintained within the register while the rest of the state machine operates in a normal manner, the control bit pattern is...