A method of testing circuitry is by the application of scan design which consists of a series of shift registers or latches which form a serial scan path through a logic circuit. The scan path can be used to observe and control logic elements in the design via serial scan operations. The present invention allows a continuous scan path to be compressed or expanded so that the scan path only passes through the desired logic element(s) to be tested. Devices connected on the serial scan path (or rin...

A unit (108) to be triggered, for example a memory, receives data under the control of Boundary Scan Test (BST) logic, via a BST chain (110). The invention utilizes a pulse circuit (202) which generates a pulse trigger for the unit (108) on the basis of a stimulus presented via the BST chain (110). This saves time, because it is no longer necessary to supply the entire pulse trigger via the BST chain and the supply of the stimulus now suffices.

A method is disclosed for generating a control signal (TMS) which may be used to control the test activity of boundary scan system (10). The method is initiated by loading a multi-bit control macro (STI, DTI or DSTI) into a register (38) whose output is coupled back to its input. After loading of the macro, its identity is ascertained by a macro controller (42) which serves to decode a multi-bit signal (IT) whose state is indicative of the macro type. The macro controller (42) actuates the regis...

In methods and apparatus for testing a digital system, system terminals used for coupling input signals into the system and output signals out of the system during normal operation of the system are connected in parallel to a single boundary register. The boundary register is operable to pass input signals and output signals transparently through the boundary register while accumulating together the input signals and the output signals. For testing purposes, the digital system and boundary regis...

An apparatus for diagnosing faults in a device equipped with boundary-scan test capability stores serial test data upon detection of a fault in a device under test (DUT). Test data corresponding to a frame vector associated with the fault is formatted so that all information from parallel tester inputs and TAP scan registers can be simultaneously analyzed. A method for diagnosing faults is also disclosed.

A partitioned boundary-scan interconnect test method for loaded printed wiring boards (PWB's) is disclosed which reduces testing-induced damage to electronic components. The method is adapted to expeditiously identify all short-circuits on a PWB. The partitioned boundary-scan interconnect test includes four sub-tests. A powered shorts boundary-scan sub-test searches for short-circuit faults between conventional nets and boundary-scan nets. A boundary-scan interconnect shorts sub-test searches fo...

Processes for diagnosing boundary scan observed data produced pursuant to boundary scan testing of interconnected circuit devices having three-state bidirectional scan cells. A first set of observed data is produced by controlling each device individually to drive the I/O pins of the device pursuant to a set of test patterns and to scan out observed values, while the three-state bidirectional scan cells of the other devices that are in the high impedance state. The observed values for each devic...

Input and output boundary scan cells respectively include latchable input and output buffers (103,40) which respectively utilize the input and output buffers of the integrated circuit in which the boundary scan cells are provided. The latchable input and output buffers provide the input and output boundary scan cells with a low overhead latching function.

A method for coupling a linear impedance control (LIC) type output driver to IEEE 1149.1 boundary scan circuitry includes entering a boundary scan load mode to load a test pattern into a chain of boundary scan registers (BSRs). The test pattern includes values corresponding to output enable and data signals according to the IEEE 1149.1 standard. Then these data and output enable signals from the BSRs are converted into test "q.sub.-- up" and "q.sub.-- dn" signals meeting the requirements of the ...

A method for detecting JTAG errors in which components in a boundary scan path of a JTAG serial test bus connect a single bit bypass register into the scan path rather than the expected register when errors are detected. JTAG instruction signals are shifted into the scan path to determine whether an instruction error was received by a component. Data scanned into the component is prefixed by a header which is monitored by the JTAG control circuitry to detect any instruction errors. The combined ...