A subsystem of binary circuits, packaged in modular form and having a plurality of connection points through which it is incorporated into a master system such as a digital computer, is tested by utilizing a binary word generator that periodically generates a string of parallel binary bits for application to the subsystem under test. Output signals from the subsystem under test are continually monitored and supplied to the binary word generator to shape the character of the succeeding string of ...

A technique of decreasing the number of test patterns required to test a MOSFET module and/or provide the ability to test elements on the module which can not be tested by conventional test techniques. Conventionally, test patterns are applied to the input pins of a MOSFET module and the output monitored at the output pins of the module. Interwoven with the normal test pattern testing is the application of a serial test pattern to selected elements on the module. The serial test pattern is appli...

A generic sequential digital pattern generator is disclosed for converting a serial data stream of n compacted pattern messages into a sequence of n parallel digital patterns. The generic invention comprises a decoding means connected to a serial data stream, for receiving a compacted pattern message and converting the message to a signal on one out of r decode lines, an output register having r binary storage cells connected to r output lines, and r modulo 2 adders in parallel. Each modulo 2 ad...

A high-speed pattern generator includes a plurality of arithmetic and logic units (ALUs) which are n in number and have m-bit outputs, n registers receptive as inputs as outputs from the ALUs, and n-bit shift registers which are m in number, each ALU and connected register being unitized and coupled to the shift registers. The outputs of the registered input data are applied to the ALUs. The unitized ALUs and registers produce outputs applied in the same sequence to bits of the shift registers, ...

A word of a test pattern is divided into blocks and stored in a storage device of a test pattern generator for testing a logic device. The test pattern blocks are sequentially provided to respective blocks of a pattern generator, which provides at respective outputs all of the blocks of a test pattern word at the same time. If a block of the pattern generator is faulty, or if another component of the test pattern generator corresponding to a block of the pattern generator is faulty, the respecti...

An electronic tester for testing an electronic structure having high circuit density, such as large scale integrated devices, system, and subsystem structures having a plurality of interconnected large scale integrated devices, and the like. The tester utilizes m words each containing n binary bits, where m is any integer in the range of one hundred through multiple thousands and n is any integer in the range of one hundred through multiple hundreds. The n binary bits of each word are respective...

A semiconductor test device including a function test algorithmic pattern generator which comprises: an ALU unit with shift-in function for conducting a predetermined arithmetical and logical operation against the base data or the output of an ALU output register; the ALU output register being designed to store the output of the ALU and output a function test algorithmic pattern; and a parity detection circuit which conducts a parity detection against an arbitrary group of bits of the ALU output...

A circuit tester and test technique are presented that compresses the amount of data stored in local test data RAMs for the implementation of a circuit test, thereby reducing the amount of data that must be downloaded to the local test data RAMs, thereby improving test throughput. Derivative data vectors are utilized in addition to raw data vectors as part of the data compression technique. Further compression results from storing only unique data vectors in the local test data RAMs and utilizin...

Thorough delay testing of a combinational logic circuit is accomplished by changing only one input at a time (a single transition), and checking the output at a predetermined short time later, and arrangements are disclosed for systematically applying to the inputs of a combinational logic circuit all possible single transitions of the binary input signals. One economical test circuit uses a conventional binary counter and an associated ring counter to generate the test signals, in addition to i...

Nodes and paths for connecting the nodes are used to form a model of at least one logic network. Next, all paths for connecting nodes in the logic network are traced, and the nodes and connecting path segments are sensitized and justified. The sensitizing patterns, when generating test patterns for a sequential circuit wherein the output is a function of a time sequence of inputs, may include a time sequence of sensitizing or input patterns for testing a single path through the network.