An apparatus and method for identifying faults in a digital logic circuit system combines the output of a feedback signature generator and a synchronous transition counter to provide a unique signature sensitive both to bit pattern timing and bit pattern sequence. A plurality of output signals of the circuit system produced in response to a preselected input signal pattern is processed synchronously through a feedback signature generator or feedback shift register network, such as a serial cycli...

This discloses a pattern generator having a programmable product cycle timer in which a pulse train, i.e., the pattern generated, having a time raster measurable to one nanosecond can be repeated or switched from a first pulse frequency to a second pulse frequency without the usual transient switching periods between pulses. The invention accomplishes this by providing the generator with a cycle timer using a ten nanosecond clock operating in conjunction with a ten nanosecond down counter so tha...

In order to set the circuit to be tested to a test mode, at least one output is led out by an output stage, and the input and output of the output stage internally leads to an exclusive-OR gate. As long as the output has a comparatively high-ohmic termination, as is the case during the normal mode of operation, the exclusive-OR gate will carry the same signal for both signal conditions of the output. For the purpose of testing a complementary pulse pattern is applied to the output, so that the e...

Electronic circuit assemblies having numbered terminals, some of which are input terminals and some are output terminals, are introduced into a test apparatus; a code combination of a predetermined program is applied to selected ones of the input terminals over an intermediate storage device and a connecting matrix. The outputs from at least some of the output terminals of the test sample are compared with outputs from a standard test sequence, or a sample of known quality, and an indication is ...

A test pattern generator comprising a memory means for storing n test pattern numbers. The memory means is responsive to a selectively alterable address means for generating a plurality of distinct test pattern sequence of numbers from the n stored test pattern numbers.

A distributed timing signal generator as a component of a per-pin architecture tester is disclosed. Start control circuits are provided per pin, and the same start signal is provided from the outside for each of the start control circuits. Each of the start control circuits then determines the start timing for at least one timing generator accommodated therein by the variable set values, and starts to control each timing generator at the thus-determined start timing. Thus, timing signals which c...

An automatic circuit tester (10) applies signals to tester terminals (12a, b, and c) by means of corresponding data channels (14a, b and c). Each channel includes a leading-edge memory 18 and a trailing-edge memory 20 that provide outputs of successive locations upon the occurrences of clock pulses applied by a clock 16 through respective phase shifters (22 and 24). A formatter (26) applies signals in accordance with the outputs of the memories (18 and 20) with a timing format determined directl...

Variable delay circuits generate output signals representing test signals having controlled timing widths. The output signals are generated by the variable delay circuits in accordance with data received from a memory under the control of a program of instructions stored in the memory. A fixed cycle clock initiates accessing of instructions one at a time. Each instruction in turn identifies control data which is supplied at times specified by a variable cycle clock. The delay circuits are assign...

A rate generator circuit for generating test signals whose timings vary in a pulse by pulse basis for testing semiconductor devices includes: a reference clock to determine a basic operational timing of the semiconductor test system; a pattern generator which stores rate data indicating timings of each pulse for the test signals for reading out a plurality of the rate data in parallel in synchronism with a system clock; a temporary storage for temporary storing and transferring the plurality of ...

A test pattern generating apparatus in which a microprogram describing a test pattern to be generated is read for interpretation and execution, address and data patterns are generated by arithmetic operations and a memory control signal is produced, the address and data patterns and the memory control signal being applied to a memory under test. The address pattern is provided to an area inversion control signal generation section to produce an inversion control signal corresponding to the addre...