A tool for the linear polishing of substrates includes an endless belt of continuous strength wrapped substantially as a helix of predetermined length and width with a 180 degree twist along the length to increase by a factor of 2.times. the time interval between which belt changes need to be made because of wear-and-tear, significantly reducing the costs associated with the polishing because of reduced down time. In a preferred embodiment for the chemical-mechanical polishing of silicon wafer s...

In a sense amp/latch, the reset/sense phase of the sense amp/latch is separated into two separately controllable operations. By separating the reset/sense phase into two separately controllable operations, the parameters associated with optimization (speed and/or completeness of reset vs. larger gain during sensing) are substantially independent of each other and therefore do not conflict with each other. The separation of the reset/sense phase into two separately controllable operations is acco...

A signal generator, such as a fractional-N PLL, has, in its feedback signal path, a divider, a phase circuit, and a fractional accumulator that generates control signals for the divider and the phase circuit. The divider control signal controls the divisor value applied by the divider. In one embodiment, a phase selector selects, based on the phase-circuit control signal, one of a plurality of phase-shifted output signals generated by the PLL's main signal path (e.g., by a multi-phase VCO) and t...

The present invention relates generally to the field of signaling of information, and particularly to a method and a system for signaling information in transmission systems.Methods for signaling information in transmission systems do have certain disadvantages, like the use of an additional channel for signaling or the use of a large number of bits for signaling.The present invention facilitates highly protected and highly reliable signaling requiring only a minimum of bits by inserting an indi...

Signal processing circuitry having parallel processing channels has clock-generation circuitry that generates (i) high-speed clock signals used to drive the channels and (ii) synchronization signals used to reset the processing of the channels. In one embodiment, the signal processing circuitry has multiple multiplexing channels arranged in one or more macrocells, each macrocell having one or more channels and a phase-locked loop (PLL) that generates a high-speed PLL clock signal and a synchroni...

A ground-or roof-top-based repeater in an OFDM system uses multiple transmission antennas to retransmit satellite signals. By using multiple transmission antennas, multiple identical OFDM signals are transmitted. Dithering is performed by, using a phase of Rayleigh process generator, introducing a slight variable-frequency phase offset to all but one of the multiple identical transmitted OFDM signals, and thus the effective overall channel is more dynamic and provides spatial diversity to minimi...

A rake receiver for processing a multi-path input signal received from a communications channel, wherein each multi-path component of the multi-path input signal comprises one or more symbols, comprises a plurality of fingers and a demodulator. Each of the plurality of fingers is adapted to receive the multi-path input signal and provide a sequence of input samples corresponding to a multi-path component of the multi-path input signal. The demodulator is adapted (i) during a single clock period,...

A telephone line driven power supply and power supply method capable of creating high yield, low voltage power using power drawn from a telephone line and supplementing the low voltage power with power from a battery-powered host device, such as a laptop PC, when the voltage level falls below a predetermined voltage level. The telephone line power supply includes a polarity guard, a gyrator, an oscillator, a pulse circuit, an inductor, a startup circuit, a converter, a shunt regulator, and a com...

In a packet-based (e.g., Ethernet) network, such as the network of central offices and base stations of a wireless telephone system, a node receives one or more incoming packet-based signals from one or more other nodes of the network and recovers a clock signal from each incoming packet-based signal. The node selects one of the recovered clock signals as the node's reference clock signal. When the node is part of a base station, the node uses the selected clock to generate and transmit one or m...

The various embodiments of the invention provide an apparatus, system and method of testing a serializer and deserializer data communication apparatus (SERDES). The serializer and deserializer data communication apparatus has a plurality of serialize data communication channels adapted to convert parallel data to serial data and a plurality of deserialize data communication channels adapted to convert serial data to parallel data. An exemplary method provides for coupling an output of a serializ...