The invention proposes an image sensor comprising a picture capture matrix having N rows and K columns of image dots, a read register at the free end of the K columns. In order to improve the read speed of the matrix, the invention proposes that the horizontal transfer into the read register be continued even while the vertical signals for shifting from one row to the other are operative, without however continuing the horizontal transfer while the transfer gate between columns and horizontal re...

The invention relates to small dimension image recorders, such as an image recorder, comprising a matrix of rows and columns of photosensitive points, arranged on a chip of a generally square or rectangular form with believed corners, characterised in comprising a reading register arranged at the base of the matrix. The register is bent to follow the bevelled corners of the chip and thus comprises a horizontal piece and two oblique pieces. The sensor further comprises means (ZI.sub.n) to direct ...

The invention relates to matrix image sensors intended in particular for digital photography. The invention provides a driver in each pixel that allows exposure control common to the entire matrix. The driver comprises five transistors, a photodiode and, apart from a supply conductor and a ground, four control conductors, these being an exposure control conductor common to all the pixels of the matrix; a row selection conductor common to all the pixels of any one row; a reset conductor common to...

The invention pertains to a comparison circuit for an analog/digital converter. In order to reduce the effect of the offset voltages of the various comparators of the comparison circuit, voltage followers and a resistor network delivering at its outputs, mean voltages that are the average of those present on outputs of the comparators are linked downstream of the outputs of the comparators.

The invention relates to integrated electronic circuits, and notably to those comprising analog functions. The invention relates more particularly to a starter circuit designed to ensure the automatic start-up of a biasing circuit following an interruption in the operation of the latter. The starter circuit comprises, in an integrated circuit substrate of a first type of conductivity comprising at least one well of an opposite type of conductivity and a semiconductor region of the same type of c...

The invention relates to wavelength-selective optical filters for allowing light of a narrow optical spectral band, centered around a wavelength (.lamda..sub.c) to pass through them, while reflecting the wavelengths lying outside this band. According to the invention, the transfer function (T.sub.1,2(.lamda.)) of the component is defined by multiplying two transfer functions of spectrally offset Fabry-Perot filters.

In digital signal demodulation and detection circuits, especially digital radio signal reception and processing circuits, the signals are received in analog form and have to be converted into logic levels. This is done in practice by comparing the level of the signal with its mean level. The mean level is established by an RC lowpass filter which introduces an inconvenient delay into the preparation of the mean level. The mean level of the signal, established by an RC filter is compared and appl...

A sample-and-hold device comprises a sampling transistor (Q.sub.ech) and a sampling capacitor (C.sub.ech), the sampling transistor being off in hold mode in order to prevent the discharging of the sampling capacitor and conductive in sampling mode to apply a voltage to the capacitor that is substantially equal to the voltage (V.sub.ech) at its base. In order to apply a cut-off voltage to this base, in off mode, that is equal to the voltage present at the sampling capacitor, there is provided a c...

A chainable adder receives bits (A, B, C) to give complementary sum outputs (SO, SO*) and carry outputs (CO, CO*). A first stage has differential pairs (P1, P2, P3) receiving bits (A, B, C), respectively, and complements (A*, B*, C*), respectively. The pairs have common output arms and are powered by an identical current (I). First and second output arms include resistors (R1, R2, R3) and (R4, R5, R6), respectively, connected-in-series to a reference potential (M). The resistors define intermedi...

A signal aliasing circuit that can be used especially to make a series interpolation cell of an interpolation analog-digital converter comprises two pairs of differential arms powered by one and the same current source connected to a first power supply terminal, each pair comprising two transistors, the transistors of one pair being parallel-connected with the transistors of the other pair. Each group of two parallel-connected transistors is connected by a respective common resistor to a second ...