A complementary insulated gate field effect transistor structure having complementary p-channel and n-channel devices in the same semiconductor substrate and a process for fabricating the structure incorporate oxide isolation of the active device regions, counterdoping of the p-well with impurities of opposite type to obtain a composite doping profile, reduction of Q.sub.ss in the isolation oxide, doping of the gate and field oxides with a chlorine species and phosphorus doping of the polycrysta...

A device for introducing a known amount of charge to a line of charge storage elements in a charge-coupled device fabricated in a conductor-insulator-semiconductor system includes a buffer charge storage element fabricated adjacent a first charge storage element in the line of charge storage elements, the buffer charge storage element having its gate electrode controlled by a logic pulse whose level determines whether charge is to be introduced to the line of charge storage elements, and prechar...

A high-voltage transient protection circuit for use in combination with a voltage regulator of the type employing an error amplifier to compare a portion of the controlled output voltage against a reference voltage and adjust the output voltage accordingly. The protection circuit can be used with three terminal positive or negative voltage regulators of either the shunt transistor or series pass transistor types. Oscillation of the protection circuit around a selected transient voltage threshold...

An improved method of MOS circuit fabrication includes the consecutive steps of formation of a selected material on the surface of an underlying substrate, removal of the selected material from selected portions of the underlying substrate, and formation of insulating material between the selected material and the underlying substrate on the surface of the newly exposed underlying substrate.

A monostable multivibrator has improved output control by minimizing the recovery time of a transistor pair and using a voltage comparator for comparing the recharging voltage of the timing network with a reference for output signal development. Recovery time is minimized by employing a Darlington circuit for accelerating discharge of the timing network in response to the trigger signal to the monostable transistor pair, whereby the voltage comparator generates an output signal which is a functi...

A process for simultaneously fabricating epitaxial resistors, base resistors, and vertical transistor bases in a semiconductor substrate utilizes the stopping power of different layers of materials to determine the location of impurity concentrations induced by ion implantation.

An improved sense amplifier circuit for a Random Access Memory (RAM) having 1-transistor memory cells which is completely dynamic in that it does not dissipate D.C. power during operation and is suitable for location at one end of a memory cell array. The trip-point voltage of the sense amplifier is controlled by a pair of capacitances. When the Random Access Memory (RAM) is fabricated as an integrated circuit these control capacitances are so structured and processed that the trip-point voltage...

A memory cell is provided which comprises a word line, a current source line, a pair of bit lines, a first transistor having a base terminal, a collector terminal coupled to the word line, a first emitter coupled to a first of the pair of bit lines, a second emitter coupled to the current source line, a second transistor having a base terminal coupled to the collector terminal of the first transistor, a collector terminal coupled to the word line and to the base of the first transistor, a first ...

A new and improved memory cell is provided which comprises a word line, a pair of bit lines, a pair of current sources each having a first side coupled to a corresponding one of the bit lines; and a bistable circuit means operatively coupled to the word line and to another side of each of the current sources, whereby the bistable circuit means assumes one stable state upon the application of a voltage on one bit line, and assumes another stable state upon the application of a voltage on the othe...

An improved memory cell comprising a word line, a pair of bit lines, a pair of load impedances, and a pair of switching transistors. The pair of switching transistors each include an emitter coupled to a respective one of the bit lines, a base coupled to a respective one of the load impedances, and a collector coupled to the base of the other switching transistor. The pair of load impedances may include a pair of transistors each having an emitter coupled to the word line, a base coupled to a re...