A method of coding in a plurality of unit coding circuit stages connected in cascade and of the same number as the coded bits comprises the steps of applying input signals to a first unit coding circuit stage, rectifying the input signals in the first stage, discriminating the polarity of the input signals in the first stage, successively applying the absolute value output signals of the first stage to the following stages for coding the absolute value signals, and converting the coded pulses of...

Input signals to a transversal filter are made random by the scrambler which is provided at the sender side. The transversal filter includes multipliers. A correlation detector having filters is connected to the transversal filter. A descrambler connected to the transversal filter converts the equalized random signals provided by the transversal filter into signals which are similar to the input signals. A connector connects the filters of the correlation detector to the multipliers of the trans...

Driving currents supplied to the current driving conductors in the hard magnetization direction axis and the easy magnetization direction axis of a thin film magnetic memory device are selected to prevent inversion of the magnetization when driving current is supplied to only one of the conductors and to permit inversion of the magnetization only when driving current is supplied simultaneously to both conductors. Readout is provided when driving current is simultaneously supplied to both conduct...

Each of a plurality of magnetic wires has a conductor covered by ferromagnetic material. The magnetic wires are equidistantly spaced from each other in parallel relation and are affixed to each other by electrical insulating material interposed therebetween.

A synchronous detecting device for detecting phase shift keyed waves utilized in satellite communications and the like multiplies the PSK signals by 2 in a first plurality of multipliers and multiplies a plurality of reference carriers in a second plurality of multipliers. The multiplied signals are applied to a plurality of phase detectors. The PSK signals and the reference carriers are applied directly to another plurality of phase detectors. The phase detectors produce outputs proportional to...

A TASI system for satellite use is disclosed in which voice signals from the individual trunks are stored prior to being transmitted and in which TASI control data are transmitted in a frame preceding the frame in which associated speech data are transmitted.

Multilevel digital signals are converted to binary signals and are transmitted as such. The binary signals are integrated by the frequency characteristic of a transmission line of narrow bandwidth. The transmission line converts the binary pulses to a multilevel signal. The receiver receives the transmitted multilevel signal and converts it to analog signals.

Data transferring means separate and independent from the central processing unit of a computer system and operating in parallel with the central processing unit transfers data between a first memory area and a second memory area in a memory. The data transferring means comprises a first register for storing the address of the data of the first memory area from which the data is successively transferred to the second memory area. A second register stores the address of the data of a second memor...

A control circuit couples the bit synchronization extraction circuit to the phase controlled oscillator of a synchronization circuit and transfers the synchronization component from the extraction circuit to the oscillator to control the phase of the oscillator when the signal-to-noise ratio of the synchronization component is at least at a predetermined level and prevents the transfer of the synchronization component to the oscillator to prevent phase control of the oscillator when the signal-t...

A discriminator circuit discriminates recorded modulated binary data signals represented in accordance with whether a clock pulse is present in the interval between bits and a pulse is simultaneously present at the center of a bit. The discriminator circuit derives a data window signal for separating clock pulses and data pulses from the input data in a manner whereby when a pulse is absent from the center of a preceding bit the data window signal is derived in accordance with a pulse present in...