A Tri-State circuit element is constructed which is uniquely suited for use in large scale integrated circuit devices wherein a relatively large number of such Tri-State circuits are utilized to drive other circuitry contained within the integrated circuit device. One embodiment of a Tri-State circuit is constructed utilizing a single NAND gate (73), a single inverter (74), a single P channel transistor (76), and two N channel transistors (77, 78) yielding a circuit having a propagation delay of...

A process for forming vias in semiconductor structures includes the step of forming a pillar on an underlying dielectric layer prior to deposition of the metallization layer. The pillar is located above the diffusion region preferably and serves to provide substantially equal distances or heights for etching vias from the top planarized surface to the metallization layer deposited over the field oxide region and over the diffusion region.

A circuit (40) constructed in accordance with this invention includes a ring oscillator (25) to provide a signal which is dependent on the propagation delays of the inverters (33, 34, 35) comprising the ring oscillator, therefore the frequency of the ring oscillator is inversely dependent upon the propagation delays of the inverter comprising the ring oscillator. Means (37) are provided to determine the propagation delay introduced by the components in the ring oscillator by measuring the freque...

A system for aligning a semiconductor wafer with a mask bearing a pattern to be formed on the wafer, in which both the wafer and the mask bear an alignment mark, and in which light used for alignment is filtered to transmit only in a selected bandwidth, uses a reflector system to gather light reflected from edges of the alignment mark on the wafer. In order to minimize the effect of erroneous alignment signals from standing waves generated when the alignment signal is reflected from a wafer coat...

A contact (15) formed in accordance with the present invention includes rounded corners on the upper and lower surface and sloped walls in the dielectric material (10) in which the contact is formed. In one embodiment, a photolithographic mask is formed above the dielectric material (10) using photolithographic techniques well known in the art. Using reactive ion etching techniques, the contact is etched until a small portion of the dielectric material remains to be etched in the contact. The ph...

A CMOS reset circuit has a reverse biased diode and a latch for latching a p-channel enhancement mode MOSFET on during the first part of the power-on cycle. The p-channel MOSFET is part of a voltage divider which also includes a resistor. When the voltage between p-channel MOSFET and resistor reach the threshold of an n-channel enhancement mode MOSFET, the p-channel MOSFET is switched off. Reset pulses are provided through one or two inverters by a load on the latch.

A modular system (30) for framing and supporting work surfaces and storage units includes a pair of generally rectangular end frames (32) having side member (36) each defining inside and outside channel sections. The end frames (32) are releasably secured together by lateral connectors (34) which are adjustably clamped along the inside channel portions of the end frame side members (36). The lateral connectors (34) are adapted for supporting storage units by means of inverted J-shaped hooks 70. ...

A high-speed CMOS output buffer reduces transient current surges and provides high output DC drive. The buffer includes a first and a second CMOS inverter connected in parallel. Each of the two CMOS inverters includes an N channel and a P channel transistor. The gates of the transistors in the first inverter are controlled by a first control inverter having a first selected switching threshold voltage. The gate of the P channel transistor in the second inverter is controlled by a second control ...

Disclosed is a digital multiplier-accumulator circuit utilizing a carry save adder tree, pipeline register and carry select adder. Also disclosed is a digital multiplier circuit including a carry save adder tree and a pipeline register.

A method to adjust the divisor and dividend, for application to a divider, so that the mantissa part of the divisor is transformed to be within a known limited range. The limiting of the transformed divisor range enables the complexity of the quotient select logic to be reduced accordingly. Once the divisor is restricted to the selected range, the dividend is adjusted proportionally so the quotient is unchanged.