A differential amplifier comprising a first amplifying circuit including a dual emitter transistor, a second amplifying circuit in parallel with the first amplifying circuit and having a second dual emitter transistor with one of its emitters coupled to one of the emitters of the first transistor and a potentiometer having a resistance element with one end coupled to the other emitter of the first transistor and its other end coupled to the other emitter of the second transistor and its wiper co...

A gain controlled amplifier circuit in which the amplifying element, such as a transistor, has its emitter-collector circuit connected to a gain control circuit which supplies a constant operating current and changes its AC impedance in accordance with an AGC signal. The gain control circuit includes a first branch having an impedance which varies with the externally applied AGC signal and a second branch having an impedance which varies with the current flow therethrough and which is connected ...

A low-noise integrated circuit zener voltage reference device including a multiple collector lateral transistor and a zener breakdown device coupled together in such a manner as to utilize the relatively poor-high frequency response characteristics and the plural current paths of the lateral transistor to substantially reduce the level of broadband zener noise appearing in the reference voltage.

A process for making a lateral PNP semiconductor device having a .beta. within the range of 5 to 500 wherein, during a heating stage, a metallic layer is left covering the surface of the wafer above substantially all of the base region separating the emitter and collector regions. The resultant effect is to cause a marked increase in the current gain of the transistor thus constructed over those similar devices manufactured in accordance with prior art processes.

Balanced mixer circuit apparatus using two matched integrated circuit field effect transistors as active elements wherein one input signal is applied to the gates of the transistors in push-pull relationship and a second input signal is applied to the substrates of the transistors in a common mode push-push manner. Both input signals thus look into capacitive loads which for practical purposes can be considered to be open circuits, thereby averting any harmonic distortion which might otherwise b...

In an emitter coupled logic transistor circuit, a plurality of data gates are arranged for multiplexing input data onto a common output means in response to a coded multiplex signal which selects respective data gates sequentially. A common current source is connected to respective ones of said data gates via the intermediary of respective current switch gates, such current switch gates being responsive to the decoded input select command signals for selectively energizing respective ones of sai...

A clocked bootstrap inverter circuit including an inverting amplifier, an active load for the inverting amplifier including a capacitive bootstrapping circuit, a biasing circuit responsive to a first clocking signal and a second clocking signal 180.degree. out of phase with the first clocking signal, and an amplifier disabling device responsive to a third clocking signal which is more than 180.degree. out of phase with the first clocking signal. The biasing circuit alternately activates and inac...

A method of simplifying metallic interconnection between the various components comprising an integrated circuit formed on s semiconductor wafer by selectively oxidizing a first set of interconnecting metallic conductors formed on the wafer surface and then forming a second set of conductors in overlying relationship with the oxidized conductors, the two sets of conductors being electrically insulated from each other by the layer of oxidation formed over the first set. The first set of conductor...

A semiconductor pressure transducer having a cavity with one thin wall diaphragm on which a piezoresistive bridge is formed of four resistors diffused into the thin wall semiconductor diaphragm and coupled together as a Wheatstone bridge, a voltage regulator including a zener diode coupled to the bridge, and a pair of nV.sub.BE circuits coupled to the bridge and the regulator circuit for temperature compensation of the bridge and regulators over the operating temperature range, each of said nV.s...

An improved three-state logic circuit for selectively providing active sourcing, active sinking or high impedance isolation of the circuit output terminal so as to develop "true" output, "false" output or third state, high impedance output signals. A first T.sup.2 L data input circuit selectively drives, through a buffer stage, an active pull-up circuit and an active pull-down circuit in response to logic input signals, and a second T.sup.2 L output disable circuit cooperates with the buffer sta...