The metal layers embedded into the contact holes of various kinds in shape are used as the lines and are employed as the lines for controlling the substrate bias. The first-layer metal line layers are made thin so as to be also employed as the lines for controlling the substrate bias. Moreover, the second-layer metal line layers are employed as the copper line layers. Thereby, a semiconductor integrated circuit which allows a high-speed and low-power operation is provided with a small area and w...

A semiconductor integrated circuit is segmented into a plurality of blocks. Each block includes a switching transistor which is connected between the CMOS circuit of the block and the ground point and is adapted to shut off the current of the CMOS circuit by being controlled by a test mode control signal, and a leakage current detecting circuit which has a self-check function for the block. A signal which is the logical sum of the outputs of the leakage current detecting circuits of all blocks i...

There is provided a semiconductor device configured as follows. On a semiconductor substrate, a titanium oxide film which is an insulating film having a higher dielectric constant than that of a silicon dioxide film is formed as a gate insulating film, and a gate electrode is disposed thereon, resulting in a field effect transistor. The end portions in the gate length direction of the titanium oxide film are positioned inwardly from the respective end portions on the source side and on the drain...

A circuit pattern, a reticle alignment mark, a bar code, and a discrimination mark which are formed on a glass plate of a photo mask is constituted of a photo sensitive and photo attenuative material containing a fine particle material and a binder. Discrimination of the photo mask is performed by irradiating predetermined discrimination light on the discrimination mark or the bar code. Alignment of the photo mask by an aligner is performed by irradiating predetermined detection light on the ret...

A semiconductor device comprising a plurality of heterojunction bipolar transistors with their base layer made of GaAsSb or InGaAs, a GaAs substrate, and a buffer layer placed between the base layer and the substrate is fabricated. The substrate and the buffer layer that lie directly under the intrinsic regions of a part or all of the plurality of heterojunction bipolar transistors are removed. Thereby, a semiconductor device using HBTs that can operate with a power supply voltage of 2 V or belo...

On the occasion of the aligning process to transfer a predetermined pattern to a semiconductor wafer by irradiating a photoresist on the semiconductor wafer with an aligning laser beam of the modified lighting via a photomask MK, the photomask MK allocating, to provide periodicity, the main apertures to transfer the predetermined pattern as the apertures formed by removing a part of the half-tone film on the mask substrate and the auxiliary apertures not resolved on the semiconductor wafer as th...

A signal to be written is transmitted to said pairs of writing signal lines in parallel with address input operation for the selection of a word line, information stored in the memory cell selected in response to the selection operation of said word line is transmitted to said pair of reading signal lines via said second selecting switch circuit so that it is amplified by said sense amplifier, and the amplified output of said sense amplifier is compared with the signal to be written on said pair...

A semiconductor memory apparatus is provided with a memory array, a first global bit line connected to a sense amplifier, a second global bit line connected to a write amplifier, and a selection circuit for connecting a plurality of bit lines selectively to the first global bit line and the second global bit line.

A power amplifier module comprises a plurality of amplifier stages, each including a reference amplifier for emulating the operation of the amplifier. The current flowing to the base of a bipolar transistor that forms each reference amplifier depending on an input power level is detected, amplified, and supplied as base current of the transistor of the corresponding amplifier.

A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETs by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at least 99.99% and Fe and Ni contents of not greater than 10 ppm, preferably having a Co purity of 99.999%.