An integrated circuit (IC) wafer container for holding IC wafers is disclosed. The IC wafer container comprises an enclosure member and a body member. The body member has one or more longitudinal openings through which the IC wafers contained therein can be pinched out or sucked out safely by using a pincer or a vacuum sucker without damaging the IC wafers.

A method of forming self-aligned transistors wherein both bipolar and field effect transistors are formed in the same Integrated Circuit simultaneously is described. A heavily doped conductive layer of one conductivity type is formed upon a monocrystalline semiconductor substrate of the opposite conductivity type to that of the one type. The conductive layer may be typically polycrystalline silicon. An insulator layer is formed upon the surface of the conductive layer. Openings with substantiall...

A method for forming multiple layer metallurgy, spin-on-glass multilayer metallurgy for a one micrometer or less feature size integrated circuit with substantially free field inversion, that is the positive charge between the first via layer and the SOG is described. A semiconductor substrate having a pattern of field effect device source/drain regions therein with a pattern of gate dielectric and gate electrode structures associated therewith and a pattern of field isolation structures at least...

A device and a method of manufacture of a semiconductor device on a semiconductor substrate including an SRAM cell with a resistor comprises forming a first polycrystalline silicon containing layer on the semiconductor substrate, patterning and etching the first polycrystalline silicon containing layer to form steps on either side thereof, forming a dielectric layer over the first polycrystalline silicon containing layer with the steps on either side of the first polycrystalline silicon containi...

A method for forming a metal contact in a self aligned contact region over a impurity region in a substrate which comprises forming a doped polysilicon layer over the device surface except in a contact area. A thin polysilicon barrier layer and a metal layer, preferably tungsten, are then formed over the polysilicon layer and the contact area. The resulting metal contact has superior step coverage, lower resistivity, and maintains the shallow junction depth of buried impurity regions.

An apparatus and method are disclosed for enhancing the operation of ESD protective circuits in a VLSI chip with a plurality of parallel CMOS devices therein, particularly a plurality of NMOS devices arranged as parallel N-P-N bipolars. In the MOSFET circuits, a number of sets of cooperating N+ regions are deposited in a P-well in a P-type substrate to form, with electrodes and connections, a set of parallel source-base-drain transistors. The ESD pass voltage is effected by different processes d...

A method for forming a chess-board patterned bond pad structure with stress buffered characteristics and the bond pad structure formed are disclosed. In one method, a multiplicity of field oxide regions are first formed in the surface of a silicon substrate. A conductive layer such as polycide is then deposited and formed on the substrate to form a stepped surface with a metal layer subsequently deposited on top of the conductive layer to form a bond pad. The stepped structure reproduced on the ...

The present invention discloses a method for forming DRAM stacked capacitors by utilizing a densified oxide layer as an etch-stop for the wet etching process of an upper oxide layer in forming a contact hole for the stacked capacitor and thus, eliminating the need of a silicon nitride etch-stop layer and the occurrence of numerous processing difficulties normally observed in such stacked capacitor forming process. The lower oxide layer can be formed by a BPTEOS chemistry while the upper oxide la...

The present invention provides a method for preventing a polycide line situated between two dielectric layers from deformation during a reflow process for one of the dielectric layers by annealing the polycide line and thereby increasing its hardness prior to the reflow process being conducted. The annealing process can be carried out either before or after the polycide line is formed at an annealing temperature in the range between about 700.degree. C. and about 1000.degree. C. in a furnace or ...

The present invention discloses a novel method and apparatus for de-etching pin-holes in a passivation layer that is deposited over a metal conductor layer on the surface of a semiconductor wafer by utilizing a substantially clear, electrically conductive film as a top electrode immersed in an electrolyte for observing under an optical microscope bubbles generated from a pin-hole on the wafer surface which functions as a bottom electrode when a DC current is flowing through the top electrode, th...