A circuit provides a restart signal to indicate a zero crossing of a continuous varying signal. A zero phase signal is generalized based on a zero crossing of the continuous varying signal. The continuous varying signal is sampled and held in accordance with the zero crossing. The continuous varying signal is converted to complementary signals, and these complementary signals are in turn converted to a signal appropriate for CMOS circuits.

A data processing apparatus capable of operating in a plurality of modes includes a technique for automatically determining the proper mode from user inputs. This invention is most applicable to small hand held or desk top data processing apparatuses which operate in one mode like a calculator and which include provisions for entering, editing and running computer programs in a higher order language. User inputs, such as those from an ordinary keyboard, are stored in an input buffer memory until...

An electronic connection socket for connecting an electronic package and including a body of nonconductive material, an electronic device fabricated upon a semiconductor substrate located upon the body. The electronic device includes several bonding pads. The socket includes a set of pins to provide interconnection to external electronic devices. The body also includes pin sockets providing interconnection to the electronic package. The pins and pin sockets of the body are also connected to the ...

For HgCdTe liquid phase epitaxy (LPE), in situ differential thermal analysis apparatus is used to precisely monitor the liquidus temperature of each HgCdTe melt. The neutral body, e.g. a slug of copper enclosed in a silica ampoule, is placed near the LPE reactor in a furnace. During heating or cooling, differential sensing of a pair of thermocouples (in the melt and in the neutral body) will show an accelerated change at transformation points, since at these points the temperature of the melt wi...

A thermal energy imaging system includes an optical system for focusing thermal energy emanating from a scene on an array of bulk semiconductor photodetectors. The detector array outputs electrical signals representative of the impinging thermal energy, a video electronic circuit and a pseudo ac coupling circuit interconnecting the detector array and video electronic circuit for reducing the required dynamic range of the video electronic circuit. The pseudo ac coupling circuit includes first and...

An MOS/LSI type dynamic RAM with single 5 V supply and grounded substrate employs a guard ring surrounding the cell array to prevent pattern sensitivity in testing. The guard ring is an N+ region biased at Vdd over a deep P+ region in a P-substrate, producing a built-in electric field which attracts diffusing minority carriers into a collecting junction. A standard process for making double-level poly memory devices is modified by adding a P+ implant and deep drive-in prior to field oxidation.

A random access read/write MOS memory device consisting of an array of rows and columns of one-transistor memory cells employs a bistable sense amplifier circuit at the center of each column. The sense amplifier is of the dynamic type in that coupling transistors connect the column line halves to the cross-coupled driver transistors. The sources of the driver transistors are connected to ground through a sequentially timed, three step grounding arrangement employing two transistors, one having a...

A control device is shown for a fuel supply system for an automotive engine having a heater which is energized, deenergized and then reenergized in sequence to heat a thermostat metal coil spring over a selected temperature range to regulate opening of a carburetor choke during engine warm up. Contacts are connected between a power source and the heater and a pair of dished bimetal elements having central apertures therein are arranged in facing relation to each other between the contacts, the b...

A video display system employs a memory arrangement for the video data which is sequentially accessed for serial read-out of the bit-mapped video information at a high clock rate, and also randomly accessed in parallel by a microcomputer for generating and updating the information to be displayed. Parallel access to the memory by the microcomputer can occur while the serial video data is being clocked out, so microcomputer I/O and video output conflict only a very minimum amount. Dynamic MOS RAM...

A semiconductor dynamic memory device has an array of one-transistor cells, with row and column decode to produce a 4-bit wide input or output. Single-bit data-in and data-out terminals for the device may be coupled to the 4-bit array input/output in a sequential mode. The row and column addresses are latched when RAS and CAS drop, and this includes the address of the starting bit within the 4-bit sequence. The other three bits follow as CAS is cycled. This starting address is used to set a bit ...